From ASM Book

Contents 1 What are Registers? 2 Why are Registers used? 3 How are Registers used? 4 Types of Registers 4.1 General Purpose Registers (GPR) 4.1.1 Accumulator Regsiter (AL/AH/AX/EAX/RAX) 4.1.2 Base Register (BL/BH/BX/EBX/RBX) 4.1.3 Counter Register (CL/CH/CX/ECX/RCX) 4.1.4 Data Register (DL/DH/DX/EDX/RDX) 4.1.5 Source Index Register (SI/ESI/RSI) 4.1.6 Destination Index Register (DI/EDI/RDI) 4.1.7 Base Pointer Register (BP/EBP/RBP) 4.1.8 Stack Pointer Register (SP/ESP/RSP) 4.2 Segment Registers 4.2.1 Code Segment Register (CS) 4.2.2 Data Segment Register (DS) 4.2.3 Auxiliary Segment Registers (ES/FS/GS) 4.3 Extended Architecture Registers 4.3.1 Floating Point Registers (ST) 4.3.2 Matrix Math Extension Registers (MMX) 4.4 System Registers 4.4.1 Instruction Pointer (IP/EIP/RIP) 4.4.2 Flags Register (FLAGS/EFLAGS/RFLAGS) 4.4.3 Control Registers (CR0/CR2/CR3/CR4)

What are Registers?

Since computers are not magic, there must be some way to physically manipulate data in the real world as indicated by computer program instructions. Registers are such data areas that are physically located on the processor.

Why are Registers used?

As stated in the last paragraph, registers are used for data manipulation. This includes mathematical operations, logic operations, program control and other various operations. Almost every form of data transfer and data manipulation is processed through registers.

How are Registers used?

Registers are used by simply utilizing instructions that involve their use. Such instructions load/store data from/to RAM, other types of Memory or even I/O Devices.

Please reference Intel's Processor documentation for specific information about instructions, their purpose and their usage.

Types of Registers

There are various types of registers that, of course, have various purposes. The following are brief descriptions of all the major types of registers found in the x86 architecture. More detailed information can be found in Intel's Processor documentation manuals.

General Purpose Registers (GPR)

General Purposes Registers are hopefully self-explanatory, registers which are used for general programming purpose.

Accumulator Regsiter (AL/AH/AX/EAX/RAX)

The Accumulator Register was initially designed to hold results from arithmetic operations, to send and receive data during I/O operations and to identify BIOS function calls.

Base Register (BL/BH/BX/EBX/RBX)

The Base Register was initially designed to be a base pointer for addressing memory locations.

Counter Register (CL/CH/CX/ECX/RCX)

The Counter Register was initially designed to perform as a counter for programmed loops and as an index number for shift operations.

Data Register (DL/DH/DX/EDX/RDX)

The Data Register was initially designed to assist in arithmetic operations and to be a pointer to I/O port addresses during I/O operations.

Source Index Register (SI/ESI/RSI)

The Source Index Register was initially designed to act as a pointer to the source of memory and string operations.

Destination Index Register (DI/EDI/RDI)

The Destination Index Register was initially designed to act as a pointer to the destination of memory and string operations.

Base Pointer Register (BP/EBP/RBP)

The Base Pointer Register was initially designed to hold the base address of the stack.

Stack Pointer Register (SP/ESP/RSP)

The Stack Pointer Register was initially designed to hold the limit (top) address of the stack.

Segment Registers

Segment Registers act as base address pointers to memory "segments" during operations that address any part of memory. These registers are apart of the x86 "Segmentation Memory Model" and are rarely used due to the advent of "flat" memory space. Despite their depreciation during the evolution of the x86 architecture, these registers are still required to have a valid values during normal CPU operation.

Code Segment Register (CS)

The Code Segment Register was initially designed to act as a pointer to the code segment in which a program is currently running.

Data Segment Register (DS)

The Data Segment Register was initially designed to act as a pointer to the data segment in which a program's variables and data structures were being accessed.

Auxiliary Segment Registers (ES/FS/GS)

These Auxiliary Segment Registers were initially designed to assist programs with addressing various segments of memory due to the the 64KB limitation of segments during 16-bit Real Mode operation.

Extended Architecture Registers

The following registers are used with certain instructions, in which the support of those instructions varies depending on the release time of the processor. Please read Intel and AMD's Documentation Manuals for more information about their instruction-sets.

Floating Point Registers (ST)

These Floating Point Registers were initially designed during the addition of the 80387 (x87) Floating Point Unit (FPU). Currently, the FPU is standard when using a 387 FPU, 487 FPU or in processors that are 586+ (Pentium and above). The FPU registers are used to store data during float-point operations of the FPU.

Matrix Math Extension Registers (MMX)

These Matrix Math Extension Registers were initially designed during the addition of MMX to the Pentium processor series. The MMX registers are used to store data during MMX operations.

System Registers

The following registers are used to control system operation and asses system/program status.

Instruction Pointer (IP/EIP/RIP)

The Instruction Pointer was initially designed to help guide program control.

Prior to instruction execution, the Instruction Pointer (IP) points to the location of that instruction in memory. During standard operation, the IP is automatically increased after the execution of each instruction.

Flags Register (FLAGS/EFLAGS/RFLAGS)

The Flags Register was initially designed to hold the state of the processor, including certain data pertaining to the currently running process.

Control Registers (CR0/CR2/CR3/CR4)

The following Control Registers were initially designed to support the enabling and/or disabling of various processor features in a programmable fashion.