And now my last point: note the relative complexity of the circuit. As Ernie says, a microcontroller would do this job easily, and possibly much more, such as having extra inputs for different coin denominations. A simple 8-pin uC, such as a PIC12C50x would do it.

This is a good point, the 12C50x even has built in RC based oscillating fuction, so you dont even need a crystal to generate a clock source. The down side is the clock freqency can vary with more error, but for debouncing circuits this is not an issue at all. I would say its an idea application for such...

Posted on 2003-05-16 18:33:34 by NaN
great thanks VVV :alright:

really make sense that you're using clock to debouncing sw, 50 Hz = 20 ms, enough time, yeah! but... i have to make the osc too, i'll try to seek info on that :)

and thanks for the complete picture, learn much from that one :grin:
Posted on 2003-05-17 06:11:34 by dion
You are welcome, dion.

As I said, the clock can be derived from the line frequency, say from a small transformer. Use a transistor with the collector resistor tied to +5V to amplify and limit the signal. That will give you a reasonable square wave clock.
A small filter may be required at the input to make sure you remove all possible HF spikes.

Good luck.
Posted on 2003-05-17 20:31:30 by VVV
hi VVV, sorry to bother again. i was took a night to think and simulating your circuit. i was dountful to the clock mechanism that would block the bouncing. i thought there must be somepoint that coin pulse/input pulse will be missing aka blocked by the clock itself. are you thinking about it too? its just because we cant determine at what time the switch would be act, meanwhile the clock is running withour care about it. i prefer what tenkey's links said. its okay, i'm gonna use a schmitt trigger instead.

and about the 7414, schmitt trigger, anyone know what the diff with normal hex inverter, besides its threshold and the type of course? i read about this schmitt, it said it took a snap-action. what does it mean? it say again that with this feature, its immune to the noise/bounce. now, how it diff with the normal gate? could someone put a timing diagram simulate all this thing together?
Posted on 2003-05-22 06:34:38 by dion
A 'standard' gate is like an amplifyer, you can make a graph of input vs output voltage out of a single line. Thats all an inverting gate is anyway, a high gain inverting amp.

A schmitt trigger input cannot be represented by a single line, as it has some memory of its current state. By this I mean say for an inverter, if you drive the input high so the output goes low, you then have to drag the input realy really low to get the output back high. For a high output you have to drive the input really really high to get the output back low.

This is sometimes called hysterisis as its analagous to how say a piece of iron wound with wire acts, you partially magentise the core and have to unmagnetise it to get back where you started.

A standard gate will have a particular point on the input where you go a little higher and the output goes low, or a little lower and the output goes high. With a schmitt trigger, you need a much larger input change to do that. Needing a larger input change makes it more imune to noise then a standard gate (but not completely immune, it has its limits too).
Posted on 2003-05-22 19:35:37 by Ernie
The simplest example of a schmitt trigger should be your thermostat in your house.

You dont want your furnace "hunting". That is firing up for a heat, and create a quick rush of heat, whitch in turn fools the thermostate that yout heated up again, turning the furnace back off. But of course you've hardly had a chance to raise the entire house temperature adequately. So almost as fast as it turn off, it turns back on again. Etc. etc. etc.

This is very hard on the furnace. But then again the control outlined here is binary. At temp X turn on, else turn off.

Schmitt triggers make it better on your house. They have a little different methology:

Temperature scale (increasing temp --> )
---- A ---- B ------->

At temp A turn on furnace and dont stop until temp B is surpassed.
At temp B turn keep furnace off and wait until temp A is surpassed.

If this was an inverter. It would work the other way as well.

<---- A ---- B ------->

At voltage B go LOW and remain low until voltage A
At voltage A go HIGH and remain high until voltage B

Here is a plot of such an invertor with schmitt triggered response

5V .|. <----->+---->---+
| | |
| ^ v
| | |
0V .|. +----<---+<------->
| . . . .
. . . . Input
0V A B 5V

Hope this adds more insight....
Posted on 2003-05-22 20:11:44 by NaN
Hi, dion,

The circuit I showed you works very well. The only way you can miss a pulse is if the pulse is shorter than the debounce time you set. This can be set by correctly choosing the clock frequency. For example, if you run it at 500Hz you will get 2ms debouncing time. So your switch has to generate a pulse which is at least 2ms wide. Isn't that practical?

As for the circuit in tenkey's link, I wanted to send you something similar.
The problem with those is that as you increase the debouncing time, your cap value becomes rather large, which is not desirable.
You can do the math for yourself from those formulas and see. In the example, the bouncing time was only 1ms, not 20ms.

Essentially, that is a filter. If you want to mask out pulses of a certain duration, you have to make sure the pulses you are trying to pass are longer that that. So this circuit can miss pulses, just like mine. It's all physics. Try simulating it and see what happens.

If you can, use the R-S flip-flop solution. That works very well and you don't have to worry about time constants. But if you don't have the 3-pin switch, you will have to choose one of these solutions.
Build either circuit. If you were to build the one I recommended, I think you would be pleased with it.
Posted on 2003-05-23 11:59:58 by VVV
One more thought:

If the pulses from the coin switch are relatively short, you can use a retriggerable one-shot, set for a period longer than the pulse width. This would be retriggered by the bouncing and give you a clean output.

Remember, the period has to be longer than the longest pulse you expect.
Posted on 2003-05-23 19:24:44 by VVV

The only way you can miss a pulse is if the pulse is shorter than the debounce time you set. This can be set by correctly choosing the clock frequency. For example, if you run it at 500Hz you will get 2ms debouncing time. So your switch has to generate a pulse which is at least 2ms wide. Isn't that practical?

see next post for the pic. in case 2, there will be a possibility that the pulse is passing the block. of course the bounce time (BT) is smaller than the pulse width. that's why theres possibility to miss one.
Posted on 2003-05-27 07:21:05 by dion
grrr.... i know this .bmp wont show up like jpgs but as link :mad:
Posted on 2003-05-27 07:44:24 by dion
From the picture I cannot tell if the input returns LOW at the end of the bouncing.
If the input stays HIGH long enough, the next rising edge of the clock will catch it and you will not miss any pulse.
If your pulses are really that short, that the bouncing doesn't stop before the "pulse" actually ends, use the retriggerable one-shot.
That is all I can suggest.
Posted on 2003-05-27 11:24:09 by VVV
hi VVV, its just my assumtion. the fact is i really dont know what the bouncing is looks like. yes, i forgot to draw the little high condition and then comes the bounce. can you draw the real one?

btw, you said "If the input stays HIGH long enough, the next rising edge of the clock will catch it and you will not miss any pulse", then you mean that the the high state is more than one clock width, isnt it?
Posted on 2003-05-28 07:11:18 by dion
Hi, dion,

Yes, that is what I mean. Take a look at the attached picture.

The first graph is the clock. The second is the input, bouncing, assumed to have the switch grounded with a pullup resistor to +5V.
The output for it is on the third plot.

On the fourth graph I shifted the input to show what happens if the clock rises right in the middle of the bouncing. As you can see, the output switches one clock period sooner or later, depending on what the data really is when the clock rises.
A similar situation is seen when the switch opens. However, as long as the input is stable for more than one clock period, the output will be clean. The dotted lines only show a delay/ advance, NOT noise. So you can have output pulses with variable width (a multiple of clock periods), but not multiple pulses.

Tb is what you call the bounce time and has to be shorter than the clock period. (Actually you adjust the clock period to make it longer than the maximum bounce time).

I think these are very reasonable assumptions. I have never encountered a situation where the bounce time is comparable to the actual pulse width. If that is the case, you almost are dealing with a train of pulses, rather than a "pulse". See the green curve. This one could be missed by the circuit.

Hope this helps.
Posted on 2003-05-28 19:43:11 by VVV
btw i was build tenkey's link way today, which is i said no ripple in the supply :grin:

but, what da... :mad: it dont work! the problem is when i bust off the chip for the circuit, it was okay and so far so good, the low is really low at gnd level. but now i am put the 7414, the low level became about 1 volt, which is i thought i was too high to be a low level. i dont have any idea how to overcome this problem. because of that 1V level, i check the output and no response anyway. its stuck low. i dont mean stuck in bad chip manner. i can guarantee the chip is *not* a bad one, because i have a tool to test any TTL chip from HI-LO product, which is so reliable i've ever seen. so, what the heck i am doing wrong here? i was follow the instruction n the make it like what it said except i using 18K resistor as R2. R1 is 1K. C is 0.1 uF. i thought the 1V level is from the schmitt trigger gate. can someone help me out?

i dont know such TI engineer would lie-ing someone stupid like me :(
Posted on 2003-06-02 06:41:24 by dion
Hi, dion,

If the gate you are using is a regular TTL gate, it will source a fairly high current into the 18K resistor when the switch is closed, hence your 1V.
I suggest you use an HC or HCT device 74HC... or 74HCT..., or 74ACT...

Alternatively you can reduce the 18K to say 1K or less, increase the cap to 1uF or 2.2uF, get rid of the diode and possibly increase the pullup resistor to 5K1. This way the first pulse will immediately turn on the gate. When the switch bounces the cap now has to charge up through the pullup resistor. But it takes time to reach the threshold, so that will debounce your switch.
Posted on 2003-06-02 11:43:54 by VVV
yes, i use 74LS14.

i'll try to increase the capacitance and reduce the R. should i get rid the diode? i just worried about the malfunction said in the sheet.

but, i dont understand how come the regular ttl gate can source in this manner? it is pulled down when the sw closed, so, i mean what the heck current to be sinked?

Posted on 2003-06-03 05:59:41 by dion
Hi, dion,

Nobody lied to you. You need to understand what really happens.

Get rid of the diode. There should not be any malfunction. Your circuit will operate much like a retriggerable one-shot. The first contact closure rapidly discharges the cap throught the now low resistor (instead of 18K use less than 1K, say 470 ohm).

Then, if the contact opens, the capacitor charges up exponentially through the pullup resistor. To reach the upper threshold, which is minimum 2V, it needs a little bit of time. This would be your one-shot time constant and has to be longer than the bounce PERIOD (not bounce time, which can contain several oscillation periods).

If the contact closes again before the end of this time, your cap will be discharged rapidly again before reaching the threshold ande generating an output, and the process repeats itself. This prevents multiple pulses at the output.

When the bouncing is finished, with the switch closed, the cap is discharged. When the switch opens, the cap starts to charge up again, but if the switch bounces, before the cap has charged to 2V, again the discharge occurs, and the false output pulses are eliminated.

If you look at the internal schematic of an old TTL gate, you will see there is a multi-emitter transistor at the input (the number of emitters is equal to the number of inputs of the gate). The base is pulled to +5V by a relatively low resistance 3.6k or so, if I remember correctly.
When your input is LOW, you actually pull low one of the emitters of the transistor. That means the gate sources the emitter current of that transistor (includes the base current, which is significant). That is, I believe, 1.6mA max. when the emitter is grounded.

Take a look at the following picture that was actually posted by Ernie, in a different thread. I hope Ernie won't mind that I am using it.
This gate only has one input. For more inputs, Q1 has more emitters.
Posted on 2003-06-03 18:36:58 by VVV
(the following is a complete digression from the current thread. Appologies to dion if I confuse anything)

(VVV, copy it as you will, thats fine. I riped it out of a data book anyway)

The LARGEST source of current OUT of a TTL input occures when there is more then 1 input. Take the previous schematic of an inverter. Now imagine the transistor has two emiters (which is exactly how a 2-input NOR gate is made). Call em A and B.

When A is high and B is low, B will supply the highest current out of the input.

WHY? Well... TTL evolved out of DTL, diode-transistor logic, where you connect the anodes of several diodes together to get an OR function (any cathode grounded grounds the common anode point), thats followed by a current driver for the transistor part of the family name. DTL exists more as discrete parts then an IC family, its a really old technology.

Multiple emmiters serve the same purpose as the diodes, in fact are made in an IC the same way. To make a diode, you make a large P well and put a smaller N well inside. The middle is the N anode, the outer ring the P cathode.

To make the emitter of a transistor, you first make a large large N well for the collector, then put a smaller P well for the base, then a small N well for the emmiter. If you make the base P well large enough, you can add multiple N wells and get the multiple emmiters.

However, look from input to input. You will trace thru a N-P-N structure. That's a transistor! Every multi-input TTL gate has these paracytic transistors, so the level of one input effects the current out of another input.

So when A is high, its the same as supplying power to the collector of a transistor, and B being low is the same as pulling the emmiter low. So inout A supplies some current that input B must sink.

Sorry for the digression, but I find the concet of a paracytic transistor to be pretty cool. (and yes, several pictures here would be very helpfull)
Posted on 2003-06-04 19:03:48 by Ernie