Hi, I find working with microprocessors quite interesting and so I decided to start with a simple PIC16F628 recommended by Maverick I think. Anyway I have a few questions:

1. IMHO Digi-keys parts qre quite on the high side in terms of price, I'll check Active Surplus in Toronto, but just in case anyone know anywhere else?

2. When I design small circuitry I will need to employ the use of Logic Gates, there are two subclasses with are TTL, CMOS (you probably already know that if u are reading this!!) anyway which should I use with a PIC/microprocessor? Schottky?
I believe I will need one with a low propagation delay and I really don't require a high fan out.


3. How would I go about calculating the resistor I need in a certain situation:

Say I have a 7V power source and I want to use a pull-down resistor to bring that power to 5V, how would I calculate the resistance needed in ohms?

4. How about the usage of capacitors?





I believe these questions are a lot to answer so if you don't feel like typing just redirect me to a site so I can read up on myself and I can ask less dumb questions :)

Thanks
Posted on 2003-04-07 18:18:45 by x86asm
Well its time to introduce theory :grin:

TTL and CMOS operate at 5V typically, but there are differences. TTL is more power hungry, but on the flip side they can operate at higher frequencies. CMOS uses very little power (only dynamic power), but have more capasitance and thus have a lower maximum frequency.

TTL consumes both dynamic and static power. This means, to hold a 5 or 0 volt level at its ouputs, it still consumes current at 5V continously. Over time, this will have a drain on your batteries, even if you never change any output levels (static power consumption).

CMOS eliminates this, cause it doesnt have any clear paths for current. Instead it relies alot on "static buildup" of sharges. For CMOS to change state, the charges have to be released from where they entered, and new charge "preasures" occur in other areas of the chip. This is like a balloon of water. You take water from the tap (power) to fill the balloon (hold an output state). There is no water being used while the output is held. When its time to change the state, the water is released from the balloon to a drain (ground). This is now used power. And some other are, another balloon fills. This is an analogy of "Dynamic Power" consumption. As energy is used only as transitions are taken. This is alot gentler on batteirs!! However, if you have a high speed clock, there is still alot of consumption from soo many changes/second!!!

So Low frequency is a design goal with CMOS for battery supported products, so battery life can be maximized.

I will answer more in a bit..
:NaN:
Posted on 2003-04-07 19:39:30 by NaN

Well its time to introduce theory :grin:

TTL and CMOS operate at 5V typically, but there are differences. TTL is more power hungry, but on the flip side they can operate at higher frequencies. CMOS uses very little power (only dynamic power), but have more capasitance and thus have a lower maximum frequency.

TTL consumes both dynamic and static power. This means, to hold a 5 or 0 volt level at its ouputs, it still consumes current at 5V continously. Over time, this will have a drain on your batteries, even if you never change any output levels (static power consumption).

CMOS eliminates this, cause it doesnt have any clear paths for current. Instead it relies alot on "static buildup" of sharges. For CMOS to change state, the charges have to be released from where they entered, and new charge "preasures" occur in other areas of the chip. This is like a balloon of water. You take water from the tap (power) to fill the balloon (hold an output state). There is no water being used while the output is held. When its time to change the state, the water is released from the balloon to a drain (ground). This is now used power. And some other are, another balloon fills. This is an analogy of "Dynamic Power" consumption. As energy is used only as transitions are taken. This is alot gentler on batteirs!! However, if you have a high speed clock, there is still alot of consumption from soo many changes/second!!!

So Low frequency is a design goal with CMOS for battery supported products, so battery life can be maximized.

I will answer more in a bit..
:NaN:


Interesting, this is the kind of explanation I'm looking for :), thanks it helps a lot.
Posted on 2003-04-07 20:06:36 by x86asm
Typical operation voltages of CMOS and TTL

TTL:
low = 0v to 0.8v
high = 2.0v to 5.0v

CMOS:
low = 0v to 3.0v
high = 7.0v to 10.0v

So you need an interface when you connect TTL to CMOS but not TTL to TTL and CMOST to TTL.

To calculate the resistance
You need a voltage divider here! Note: When designing circuits, always assume an already available value of resistance in the market...for example, assume R1 to have 270 ohms!

R1 R2
Vsrc -----\/\/\/----\/\/\/----Gnd

Vsource = 7v
R1 with 2v voltage drop
R2 with 5v voltage drop (your load, i guess)

so solving for R2 in terms of Resistors and Voltages...
V2(of R2 -> 5V) = (Vsrc x R2) / (R1 + R2)
R2 = R1 / [(Vsrc/V2) - 1]

R2 = 675 ohms!

just play around with the equation!

Usage of capacitors
There are a lot of usage of capacitors!!! It depends on how you're gonna use them!
1] It can be used for filtering (high/low pass filters)
2] time constant (t = RC)
3] eliminate transient voltages (shunting your powersupply with a capacitor)
4] so many others! ;)

HTH
Posted on 2003-04-07 20:32:44 by tachion
Im trying to keep this all simple, so people can relate without having to boggle done in numbers and formula.

Capasitance: If voltage can be seen a the road a car drives on, capasitance is the shocks in the wheels. The higher the capasitance, the 'stiffer' the more sluggish the shocks are (and the bumpier the ride). VOLTAGE ACROSS A CAPASITOR CAN NOT CHANGE INSTANTLY AND ABURPTLY, instead the voltage will rise and decay exponentailly in time.

In the above discussion with CMOS. This should now show why they dont operate as well at high frequencies. Their internal capasitance being much higher than TTL implies outputs can not change Voltage states as fast as TTL does.

The buck doesnt stop here either. Your loads on the output also have their own capasitance. This in turn will make the CMOS's max fequency to be even lower yet.

Dont get all to bent outa shape over this tho! Its only for understanding of the principal that is capasitance. You have to be a very high frequencies anyways to feel these effects. Most "beginner" projects will never even get close to these concerns. (unless your designing a new cell phone ;) ).

The mathematical principal with capasitance is:

dV/dt = 1/C*dI/dt

or integrated to be:

V = 1/C * Q

Where Q = Charge in colombs, V = Voltage, C=Capasitance, I=Current (d = "change in" a.k.a. partial derivative)


Physical Capasitors:

Physically they come in many forms. Ceramic, and dialectric are the two most common. Each with their own properies. Ceramics tend to be smaller maxing out around 1uF. (micro-Farad), however they are not polarity sensitive.

Dialectric capasitors are polarity sensitive, but can get very big! 1 000 uF or bigger!. They dont get too small tho, about 0.01 uF is the smallest i've seen.

How a capastor is made is by making a BIG surface area of conductive material. Then copying this and placing the two parallel copies very close together without touching. This "teases" electrons. When a capasitor is charged, one surface feels positive force, and the other negative. Electrons rush in "feeling" strong positive force, but hit the wall realizing there is not direct path to the positive. The magnetic attraction keeps them trapped pushing against the surface's edge, hoping to get accross to the other side. Voltage appears across the capasitor as more charges (electrons) are held onto one surface.

To keep the charges from jumping across. An insulator is placed between the two surface plates. It must be a good insulator, but also be very thin. Ceramic does this well. Dielectic capastors use an oil and special surfaces. However, if the voltage is applied reversly. Charges will rage across the oil, heating it up, and will eventually boil. This creats gas, and BOOM your capasitor blows up!. (And it stinks like A$$ too ~ trust me!). This is why most dielectric capasitors have a break "V" etched in the top of them. To ensure they blow upwards and controlled (if they have to!).

As well phisically, the reason voltage doesnt change instantly can also be seen as all these charges being people rushed up against a fense wanting to get through. When a connection is made from the positive to the negative, there is an alterate path!! TO go around the fence!. However the alternate path is small, a small tunnel in a sea of people. And not everyone can get through this tunnel at once. It will take time to file everyone through. This is what happens with charges on a capasitor when its asked to charge and discharge. The tunnel has limitations (resistance of the connection), and the number of people it can fit on the surface (open field of people) also refered as CAPASITANCE.

Since capasitance if a funtion of how big the field is for people to rush in on, its should be natural to assume that to put to capasitors in parallel (to fields beside each other), the total capasitance is the sum of each (total area of the two fields). Well this is exactly how it is!:

Capasitors in parallel:

Ctotal = C1 + C2 + C3 +...+ Cn

Inversely, Capasitors in series (much harder to envision so i wont try) are:

1/ Ctotal = 1/C1 + 1/C2 + 1/C3 + .. + 1/Cn


Tomorrow i might talk about resistors or inductors ;)
:alright:
NaN
Posted on 2003-04-07 20:34:31 by NaN
Either TTL or CMOS will work with a PIC. I'd ask you what you are trying to drive before offering an opinion on which to use.

Using a resistor to control the supply voltage is a poor way to go. You might coax a 3-terminal regulator to do this. While some of the newer ones need very little headroom to operate, 2 volts should be plenty for even a 78L05, which will drop a lot more.

IF you were using the resistor, you'd pick it like this: You know the voltage, its 7 - 5 volts, or 2 volts across it. You need to know how much current the PIC (and anything else using the 5 volts) draws, lets just guess its 15mA. We can compute the resistor from ohm's law:

E 2
R = -- = --- = 13.333 ohms (not a standard value)
I .015

P = I*E = 2 * .015 = .030 watts

However, note this is very dependent on current. If your project say lights a LED, that 15 mA will change by the LED current, which could double or more. Yikes, at 30mA, your 5 volts is only 3 volts. This might even cause a POR (power-on reset).

Lazy man's guide to caps:

1) Put a .01uF ceramic cap from Vcc to Vss (or Vee) on every chip you can. If you scrimp, make it the simple gate ICs, every complex gate, or gate driving a load current shall get one.

2) Put a big cap as the power enters, 10uF or so. Electrolytic or tantalum. Tants are better at high frequencies, but both could use the help of a parallel ceramic cap at the same place (.01 again)

3) 0.1 uF instead of .01 caps may help you sleep better.

4) Never use a cap at more then half its voltage rating. If its a 25 volt circuit, put a 50V cap there. It will last much longer this way. Try not to use one less then 1/10 the voltage either, or no more then 100V rating in a 10 Volt circuit, they just act weird at higher frequencies.
Posted on 2003-04-07 23:26:53 by Ernie

Hi NaN, first of all congrats for your writing style, which is very clear and good. :)

Just one note:
The magnetic attraction keeps them trapped pushing against the surface's edge, hoping to get accross to the other side.
Forgive my ignorance if I'm wrong.. but shouldn't magnetic be replaced with electric? Or are there significative magnetic effects in capacitors?
I thought those were significative only in inductors (where, per contra, electric fields aren't as significative).
Was I wrong then?

PS: just one suggestion.. wouldn't it be more "visible" to put these informative posts in a independent thread, and then in a FAQ for the Electronics forum?

Keep the great work!! :alright:
Posted on 2003-04-08 01:59:07 by Maverick
This stuff is more interesting to learn than programming >=|

All the posts have been very useful I am taking down notes
and will refer to them while I design the circuits :)
Posted on 2003-04-08 07:31:00 by x86asm
I will clean these posts up in time... (I have yet to ask Hiro to give us a FAQ section... but i dont think he will fight us on this request).

As for your correction. You are 100% correct. (Your really do want me to get into Maxwell's equations, and all things alike! ;) )

Magenetic fields (the "H" field) is created from moving charges (current).

Electric fields (the "E" field) are from static charges on particals.

In my above description, magnetic fields give the reader a better idea of the action (cause we all know magnets), but to be true the fields holding them along the surface is from static electric fields.

:NaN:
Posted on 2003-04-08 19:13:09 by NaN

Thank you.. I'm self taught and I had the (very unpleasant) doubt of having wrong bases since long ago. :)
Maxwell would be great, someday, when you have the time and wish.. and certainly it's nothing prioritary, since a lot of water has to pass under the bridges before electromagnetism becomes the next natural thing to learn.

Anyway, keep the great work. :alright:

This board is simply the best in the universe.

We even have a recipes thread. :grin: :grin: :grin:
Posted on 2003-04-09 04:49:51 by Maverick
Man this stuff is good.

Keep it coming.


:alright:
Posted on 2003-04-16 22:08:44 by IwasTitan
TTL:
low = 0v to 0.8v
high = 2.0v to 5.0v

CMOS:
low = 0v to 3.0v
high = 7.0v to 10.0v

So you need an interface when you connect TTL to CMOS but not TTL to TTL and CMOST to TTL.


It's been a long time so correct me if I'm wrong.

The CMOS outputs depend on the supply voltage. You can run cmos at 5v from the PS supplying the ttl. The interface to the cmos need not be anything sophisticated however. Since a low in ttl is .8v (I thought it was .7v, a diode drop), it will work with a cmos low. It's the high that will get you, however, since a ttl high will not go over 3v (typically, 2.7v I think, but NEVER 5v since that's a short to the 5v rail, unless you are using open collector (OC), but I digress).

The solution is simply a pullup resistor on the ttl output. I think 2.2K works good but it has to be larger enough so the gate can pull the extra load (current through the resistor) down below the cmos low threshold.

Off the top of my head I can't remember cmos to ttl conversion but I have to leave anyway. I think I used to use OC gates to do that but, like I said, I forget.:(

The most "high tech" I got was using PALs and started learning gate arrays. Otherwise I did all ttl/cmos and transistor/rf/audio design.
Posted on 2003-04-17 16:37:53 by drhowarddrfine
Your TTL envisionment is not exactly accurate.

First, your TTL low is Vce(Sat) ~= 0.2V . Your thinking of Vbe, the diode base to emittor drop.

Secondly. On a chip, such as the 7404 with TTL, there is both NPN and PNP transitors at work. When a +5 is to outputted, a PNP transistor network is active, and saturates to the same ~0.2 V drop. So you sould get 4.8 V output. Likewise when a 0 is to output, the NPN network saturates, and ~ 0.2 V is the output.

Its quite interesting really to design TTL devices, there is a total mirror of NPN and PNP networks, except the operators are reverse:

If I want "(A and B)": (0V out) The two NPN transistors are in series to ground. And (5V out) two PNP transitors are in Parallell to +5v rails), then through the invertor, to make an AND gate. If i want a NAND, then no invertor ;)

Not Gate


----- 5V -----
|
-- PNP
In | | out = !(In)
----| |-------
| |
-- NPN
|
----- 0V -----



A . B (AND)

----- 5V -------------------------
| | |
A-- PNP B -- PNP -- PNP
| | !(A.B) | | Out = A.B
|-----------|-------------- ---------
| | |
A -- NPN -- NPN
| |
B -- NPN |
| |
----- 0V ------------------------


Dont do this at home tho, you'll burn out your transistors with out proper biasing resistors that are not shown here.

:alright:
NaN
Posted on 2003-04-17 18:17:38 by NaN
You're right about the low being 0.2 but my TI data book shows a diode, a resistor and a transistor between the +5 rail and the output. They guarantee 2.4v for the high with 3.0v typical.
Posted on 2003-04-17 18:57:47 by drhowarddrfine
Well i dunno then.. my chips always read 5V when measured. I leaned this in school. As explained, it was applicable to both TTL and CMOS technology for designing gate logic circuitry. How Texas Instruments does things is must simply be another can of worms... (Me shruggs)

Also, are you sure your not looking at the min value of a High output?? This looks like the min voltage for high outputs with a large amount of loading on the signal. More current loaded through the chip means more effect the voltage divided takes (between this internal resistor, and the external load(s)). There will be a point at max rated current, the internal voltage drop will be approximately 2 V, leaving 3V out as your "high" logic...

Even with your resistor and a NPN transitor, a high output, unloaded should be 5v (since there is no current draw asside from a few nano-Amps of leakage through the transistor). At low output, there is full current across the transistor (4.8V / Resistor value), and a output of Vce sat due to the voltage drop across this resistor.


:NaN:
Posted on 2003-04-17 19:22:53 by NaN
TTL will have a very solid near zero low output. The high output is a little shakey, it's just not designed to go to Vcc. Here's a 7404 inverter right from the TI datasheet (refernce designations are mine):



For the low, Q4 is being driven by about:

B(Vcc-3Vbe) / R1 as Q1, Q2 and Q3 all act as B-E drops, and Q2 gives it gain. Thats gonna get another B multiplier on the collector of Q4. So a solid zero.

For the high output, cross out Q2, and Q3 is being driven by:

B(Vcc-2Vbe) / R2

still enough current, BUT... it comes thru 2 Vbe drops. So as soon as you take a small ammount of current here, the output will drop by 2Vbe, call that 1.4 volts. 5-1.4=3.6, and we havn't drawn any real current yet.

The moral is if you want to drive CMOS from TTL, use an output that just drives CMOS (so it has no DC load current), and put a pull up resistor there anyway. 2.2K or so.

TTL is usually quite happy to be driven from CMOS, keep it to one CMOS output driving one TTL input (TTL inputs do sink and source current).

(Huh? An input sourcing current? Yep... but thats another thread)
Posted on 2003-04-17 21:08:52 by Ernie
Hooked up my son's 300 in one project lab :grin: and I get an unloaded 4.0v on a voltmeter using a 7404 by National Semi.

Yes, the 2.4v are minimum (guaranteed) highs and the 3.0 is typical on the sheet. You have to design using the 2.4v number for large scale manufacturing but for smaller production numbers you can use typical.

I found the typical propogation delay number worked for all the chips I used when prototyping. I remember having to redesign some video logic when the fanout on a couple of signal lines would slow them down. Most data sheets, at least then, won't tell you what the input capacitance is on ttl gates. I finally found it and could easily calculate the delay just by the number of gate inputs on the same line.
Posted on 2003-04-17 21:47:47 by drhowarddrfine
Well i stand corrected regarding TTL, i guess. I definiety know CMOS operates with this structure, and i could have sworn it was the same approach to TTL gates.

Thanks for correcting me here..
:alright:
NaN
Posted on 2003-04-17 22:53:08 by NaN
NaN,
I think you are correct with cmos. I didn't look closely at your drawing but I think it is correct for cmos. It will pull close to the rail for a high and low but they don't use the same structure for ttl.

Like I said, I'm embarrassed how much I've forgotten due to lack of use so I have to check everything I say.:(
Posted on 2003-04-17 23:04:09 by drhowarddrfine
LOL,

Thats my mistake, often im rambling from memory as well. Consulting Engineering doesnt keep your practical skills up :rolleyes: . Maybe when this economic slump is over, i can find a good hands-on electronics job. But since Nortel dumped its brain-pool into the open market there is no chances for receint grads like myself. Heh, 10 year PEng's from Nortel are now doing Secritary work in some places... :yikes:

:NaN:
Posted on 2003-04-18 09:29:13 by NaN