I've done a lot of googling with little results.

I would like to program CPLD with an embedded controller, but I don't want to use (x)svf (script file for bit banging the JTAG port).

I also want to download the JED file into the board, where it will be parsed at download time into a binary format.

Any information CPLD burners (such as interpreting JED files and device types) and ISP/JTAG signalling is greatly appreciated.

Posted on 2003-04-15 22:18:29 by eet_1024
Maybe i have been consulting for too long, but i dont have the foggiest idea what your looking for.... ( Me Shrugs )
Posted on 2003-04-16 18:00:39 by NaN
Most CPLD, PLD, etc equation assemblers and compilers produce JEDEC (*.jed) files that contain the programming that is burned into the device.

JTAG is a serial protocol originally design for in circuit testing, but is commonly used to program CPLD's, FPGA's, and some GAL's.

The XC9536 is a low power, 36 macro cell CPLD manufactured by Xilinx.

The programming (burning) software provided by Xilinx is not design for production; it degrades with each CPLD that is programmed, forcing me to relaunch it after 10-15 burns.

Since I'll be design testing software and hardware, I would like to incorporate programming capablilities into the tester.

I need information on how to parse the JEDEC file, how the data in the JEDEC file relates to the XC9536, and how to program XC9536 using a JTAG port.
Posted on 2003-04-17 00:37:13 by eet_1024
Found the spec' for JEDEC files http://www.jedec.org/download/jedec/jesd3-c.pdf
Posted on 2003-04-17 00:54:55 by eet_1024
Well I have used Xilinx before in school.. Cant say i was impressed with it. Found its software front end for FPGA' very frustrating to design with.

I Hope its come alone since then.... they certainly have potential..
Posted on 2003-04-18 23:38:40 by NaN
Yeah, I don't think xilinx should be in the software buisiness.

For those wanting to know:
ISC - In System Configuration
ISP - In System Programming

SVF - Serial Vector Format:
Contains opcodes and data that describes how to bit bang the TAP (Test Access Point)
Generated by the xilinx programming software

XSVF - Binary version of SVF
Created by svf2xsvf.exe

xsvf2ascii.exe produces a text file that is more readable than SVF

Some (somewhat usefull) documention:
http://www.xilinx.com/xapp/xapp058.pdf - Xilinx In-System Programming Using an Embedded Microcontroller
http://www.xilinx.com/xapp/xapp069.pdf - Using the XC9500 JTAG Boundary Scan Interface
http://www.xilinx.com/xapp/xapp503.pdf - SVF and XSVF File Formats for Xilinx Devices
http://www.xilinx.com/support/sw_bsdl.htm - BSDL Files (contains opcodes for ISC opcodes)

I've been comparing XSVF files (compressed (uses XSDRINC) and non compressed (XSDR)) to the JEDEC file.
Figure 6 of xapp069 shows how the 27 bits found with the XSDR instruction (of the non compressed XSVF) coorelate to each 8bit word in the JEDEC file.

The *.xbl file is useful for matching up addresses in the XSVF

The IEEE standards involved are:
IEEE Standard Test Access Port and Boundary-Scan Architecture(doesn't cover actual programming)
IEEE Standard for In-System Configuration of Programmable Devices (describes the FPRG, FVRY, FERASE, etc)

I need to generate and review the *.ics file (should provide more info)

I called the xilinx hotline, they ended up e-mailing a doc describing the non TAP prgramming method (CPLD pins used as address/data)
Posted on 2003-04-19 05:28:13 by eet_1024

:grin: You talk about Xilinx... I wondered if I could buy a Xilink (or other FPGA) board to help me with time-consuming routines. I mean : having a basic Win32 EXE that calls the FPGA board for SPECIFIC parts of my program.

Impossible ? Tricky ? Unefficient ? The frequencies are low, maybe 650 MHz for the best case, but if it can handle *many* operations in parallel, who knows. Most of my routines are a collection of recursive binary operations, highly "parallelizable", that I may transform to iterative ?!?!

You don't seem to be enthusiastic about FPGA : is it the programming AND the performance ? No better choice than AMD/Intel ?! I am looking at other alternatives : SMP/x86-64/"Internet shareable program", most probable is *great* x86-64.

Posted on 2003-06-27 07:10:16 by valy
I believe FPGA's are mostly used as glue logic. In my case, to support a 16MHz processor.

A high speed DSP might be what you're looking for. TI has some that run at >1GHz.
Posted on 2003-07-10 00:15:45 by eet_1024

Found the spec' for JEDEC files http://www.jedec.org/download/jedec/jesd3-c.pdf

uhm... i dont find such :(
just this :

Published: Jun-1994
This standard was developed to prevent the proliferation of data transfer formats that occurred with microprocessor development systems. The focus of the standard is on field programmable devices and their support tools. It is not intended for other types of semicustom logic devices or other types of fabrication or testing equipment.

did u refer to jeds file format? or i did wrong?
btw, i am looking for fuse map file format, any idea/link?

Posted on 2003-08-16 02:57:39 by dion
Looks like it moved or was pulled.

A quick google found ftp://icarus.com/pub/eda/doc/jesd3-c.pdf

You may also do a search for PLAN2 -- used to compile equations into fuse maps.

If you want to program a device, you will need to know the protocol for that device.

XILINX provides the info for parallel/high voltaga programming.

Using JTAG is pretty much the same thing, except in a serial format (haven't tested this).
Posted on 2003-08-16 05:06:17 by eet_1024
Posted on 2003-08-19 03:18:07 by eet_1024