hi all, i wanna to ask/discuss about diagnose ttl chip, type 74245 and 74161/163 .

okay, lets go to the 161/163 bin counter first. i read about the sheet a little bit, and here what i got , i often seeing this chip was used withour load feature, so, in my reasoning, there will be no condition where only 2/3/4 of out pin which pulsing. the possible condition if only one of these pins pulsing is only Q1. if its on Q2/3/4, then somehow its wrong behaved. and if none of those pins pulsing, and sure that its not using load pin, then the chip is burned out and got to be replaced.
nah, if the load is used, then outs will be the same like ins .

then the 245 bidi buffer. i dont understand everytime i seeing the ins and outs of this chip. should it be just a buffer? then should the ins pulses will be the same like outs pulse? but the fact is not like that :( the problem is i noticed the pulse on one side was usually wierd, not like the other side. its like a 'bad' pulses in those pins. i was thinking, is it because of tri-state buffering? but, if it is, i have no clue why it can be like that. anyone can explain this?

Posted on 2003-07-05 02:48:35 by dion
The '160 I beleive is a version of '161. It is a decade counter. The purpose of the load pin is the counter can be jam loaded asynchronously with the inputs of A,B,C,D. That means when ever active low load input pin is driven to a low level the ABCD inputs are jam loaded into the counter and the count will continue from that value with each clock cycle. You could use some combinational logic at the Q outputs to drive the load pin so that the count never starts at zero.
The'245 is a buss driver, yes buffer. It isolates the load from the sourrce of the data signals and amplifies it's output signal so it could drive several loads. This is known as it's "fan out" capability.
Posted on 2003-07-06 16:57:57 by mrgone
Hi, dion,

The 161 can be preset, or loaded with the data present on the A/ B/ C/ D inputs, when the /LOAD input goes LOW. When the /LOAD signal is HIGH (inactive), the circuit counts CLOCK pulses. Even if the load feature is never used, all outputs will sooner or later "pulse", with a clock signal present. That is because the circuit counts, so the output code must change. If under these conditions one of the outputs does not "pulse", the circuit is defective.
However, you should make sure you waited enough clock cycles (16) before you decide that it is not working. Also, you should check that the /CLEAR signal is not driven LOW by something, because that would reset the counter and the higher rank outputs would never go HIGH and so you would believe the circuit is defective.

To summarize, with /LOAD signal HIGH, /CLEAR signal HIGH, given more than 16 pulses at the CLOCK input, each output (Qa, Qb, Qc, Qd) must "pulse".

As for the 245, this is a bidirectional buffer with tri-state outputs. So the "ins" and "outs" can only be the same while the /G input is LOW, otherwise the "outs" will be tri-stated, so they will be different from the "ins". And since the circuit is bidirectional, the "ins" and "outs" can be reversed, depending on the state of the DIR (direction) input. Therefore, deciding that a circuit like this is working or not is not a trivial task.
Generally, trigger your scope on the DIR or /G signals and compare the "ins" and "outs" ONLY while the DIR and /G signals are in a stable state.
Posted on 2003-07-06 20:02:48 by VVV
thanks mrgone and VVV :)

To summarize, with /LOAD signal HIGH, /CLEAR signal HIGH, given more than 16 pulses at the CLOCK input, each output (Qa, Qb, Qc, Qd) must "pulse".

i got what you mean mrgone, that is adding whatever combinational circuit at Q to drive the load/clear/preset. okay, maybe i dont always check the input. VVV, you said that all Q *must* pulsing. so, now, how if i add something so the count will overflow at n. say the n is 2, so, i guess only QA that will be pulsing. this is what i mean to ask. i dont want care about other combinational circuit, but wanna to know, is it all Q must be pulsing to know whether the chip defective or not?

now, my brain works a little bit. how about n=3, so it wont raise to 3, thus only QA and QB that pulsing, is this right or wrong?

btw, i cant count how many pulse, because i do it on the board directly, you know that :)

uhm.. is it possible that only QD which is pulsing? using preset? can it cound down?

Posted on 2003-07-07 05:55:31 by dion
Hi, dion,

If the circuit is loaded with a code and then incremented, if there is no other circuit to clear/ preset it again, the circuit will continue to count and so ALL the outputs will pulse.

If there is any combinatorial circuit that clears/ presets the counter, you may not see all the outputs pulsing. Therefore you MUST make sure you know what resets/ presets the counter in normal operation, before you jump to any conclusions.

If there is NO such circuit and some outputs are stuck LOW, then the circuit is defective.
Posted on 2003-07-08 18:49:18 by VVV
thanks again VVV, i'll check that each time i got to...
Posted on 2003-07-09 05:47:16 by dion
This is the timing diagram of a 4 bit binary counter such as a 74HC191. The counter is configured to count down by configuring UP/DN pin. The counter is nothing more then 4 cascaded D type flip-flops. Each flip-flop uses the prior flip-flop as it?s clock source. On the clock?s low to high transition the first flop-flop will change state. QD is the most significant bit and QA is the least significant bit. As you can see the ?191 counter is counting down from 15 (hexidecimal F) to zero. You should be able to finish this diagram yourself.

I wish I new how to cut and past a graphic on this board. You'll have to download the graphic I'm afraid.
Posted on 2003-07-09 11:36:41 by mrgone
Hopefully this came out OK
Posted on 2003-07-09 16:43:15 by mrgone
thanks mrgone :grin:
i not mean to ask that. sorry if i often make you guys misinterprete my question. i'll try to refine next time :)
Posted on 2003-07-10 05:53:28 by dion