I want to know what makes NAND gate such a usefull. BTW how one can store data with NAND gate as i know you need 2 NAND gates to do this but how is it working ??
Posted on 2004-01-09 18:16:37 by AceEmbler
Simple:

with NOT AND and OR gates one can make any kind of binary logic IC/functions

NOT and AND are in the NAND gate, and you can somehow make OR via clables/cabling
Also usually in IC the CS and other important signals like WR/RD are negated hence the NOT included

but OR gates and demux/mux/decoders are also pretty much used (even sumators)

2NAND gates can create a FLIP-FLOP== the basic element of static RAM memory chips
there are some flavours for flipflops:R-S, J-K, and D being the most usesd

Basically a flip flop keeps its states after a transition is forced via input signals and by doing so
it serves as a memory of the bit 1 or 0 we wanted to store inside.

Besides Memory, other usages for flipflops are:counters.incrementors/decrementors/shifting registers
filtering multiple false transitions in input signals, buffering

The flip flop uses "positive" reaction to achieve its function (for memory at least)
That is the forced output is then returned to the input and in doing so it becomes self sustainable with no refresh required (but power supply of course). With some speedy improvements they are usually the fastest memory available in small quantity.

However please note that modern/today memory is more like a capacitor using a single transistor in MOSFET technology... (NMOS/CMOS/etc) But they pay a heavy price: they require constant refresh, and usually RAS/CAS sequences slow them down additionaly 2x.

Flipflops are still used in cache and static fast ram...
because they use up too much space and power/heat
to be used in comercial CPU... but have been used as such in initial CPU's
Posted on 2004-01-09 19:09:32 by BogdanOntanu
WOW thx a lot :alright:
Posted on 2004-01-09 20:10:09 by AceEmbler
AceEmbler,
BOTH NAND and NOR gates are considered "universal" gates, because any digital system can be implemented solely from either one of them. They are duals of each other. They gain their usefulness from their inverting property, which cannot be duplicated with only AND or OR gates. Any digital system can store data if it latches in two or more states. Latching is accomplished by feedback from the output of one gate to the input of a previous gate. A simple flip-flop (a two-state latching circuit) can be easily made with two NOR gates or two NAND gates. Consult a elementary logic design book for details. Ratch
Posted on 2004-01-10 10:40:59 by Ratch

However please note that modern/today memory is more like a capacitor using a single transistor in MOSFET technology... (NMOS/CMOS/etc) But they pay a heavy price: they require constant refresh, and usually RAS/CAS sequences slow them down additionaly 2x.


The RAS/CAS sequence does not slow anything down.

This argument was given in the early '70's by TI (and others) when Mostek invented the multiplexed (RAS/CAS) system. The advantage of the multiplexed system is that it cuts the number of address inputs in half.

The multiplexed/unmultiplexed "war" lasted about a year and the MosTek (multiplexed) guys won hands down. Since that time, all dynamic RAMs are multiplexed.

If this scheme would have slowed anything down, it never would have prevailed.
Posted on 2004-01-11 16:46:41 by msmith
I learned interrupts on MK3881
Posted on 2004-01-16 16:35:29 by mrgone
msmith,

Well, with 1/2 number of the pins/lines for address lines please tell me how on this earth it there possible to address the memory without sending first RAS and then CAS signal at a latter time? Multiplexed means exactly that: "multiplexed in time" aka there will be some time loss :grin:

Yes i know that there is possible to emit RAS and them multiple CAS signals to speed things up but not for all adresses in RAM...

This RAS/CAS will slow down RAM a lot besides the need for constant refresh also slows them down and/or complicates logic a little. That is why static and full address (no RAS/CAS) cache memory chips are much faster but also cost a lot more and require much more power and... see below

This "slow" memory (well slow only when compared with faster static/normal ram) won out because of some factors:
1)huge sizes on the same chip area
2)1/2 pins needed (yeah pins cost a lot in IC)
3)lower power comsumption/heating

The static non RAS/CAS memory is still a lot faster (aka 10x at least) --> hence the CACHE idea.

In a capitalistic world costs and profits matter much more than absolute truth :grin:
But you do not heve to belive them also do you?

Besides size of RAM is an important performance issue not only speed...
as everybody wants 1G of RAM at 400Mhz and not 4Megabytes at 4Ghertz... dont they?


If this scheme would have slowed anything down, it never would have prevailed.


Why? and by who's standards? By your own mind/logic standards? Only what costs less will prevail :tongue:
Posted on 2004-01-16 18:29:16 by BogdanOntanu
BogdanOntanu,

All of your examples compare the RAS/CAS dynamic rams to static rams.

My point was concering the early TI style dynamic rams that presented all of the address bits broadside. This was also a clocked dynamic ram (not static). My remarks were not to the one ras-multiple cas type cycles as these are not general purpose.

The clocked (dynamic) (NOT STATIC) rams had simpler clock timing than the Mostek multiplexed types but this did not result in faster access times.

I have done over thirty dynamic ram designs since the seventies for my own firm and contracted to others. Most of these were high performance TTL (not LSI) designs. Some the designs even used odd/even refresh so that if the processor was accessing an even address, the odd addresses were refreshed (and vice versa). This scheme required 2 sets of address multiplexors and consumed more power, but provided transperent over-refresh (which eliminated the alpha particle problems in the dymnamic cells).

The Mostek design so badly buried the TI design in the seventies that apparently you were not even aware of them and thought I was referring to static rams. My previous post never mentioned static rams (which you seem to be defending)
Posted on 2004-01-16 20:03:56 by msmith