hi all,

i'm trying first z80 simple proggies.. without success :(

I've this easy code to test if IOREQ pin go LOW on the OUT instruction cycle..




org 0

; *******************************************
; out instruction functionality test
; *******************************************

start

; 4Mhz, 20 msecs to wait for LCD startup

ld e,27
p201 ld d,255
p202 dec d
jp nz,p202
dec e
jp nz,p201

ld a,0x30
out (1),a

nop
nop

jp start



I've just Z80 and one eprom, so no CALL have been using since ram is missing.
The issue is that with my old oscilloscope i only see nice signal on RD pin but nothing at all on the IOREQ that i need caose i want drive an LCD. IOREQ is always high. A strange thing is that the _WAIT that's now left disonnected is low..
Hope in some good anime help :) B7
Posted on 2004-01-31 11:05:13 by Bit7
mm probably i'm missing something... :(

this is what i see on the data bus...

probably the istruction fetched is wrong.
Posted on 2004-02-02 07:08:05 by Bit7
I don't like unconnected control inputs, especially with MOS devices.
Connect these inputs to +5V, either directly or with a resistor (anything up to 10k)...

/BUSREQ - high prevents CPU going into 3-state (DMA, inactive) mode
/WAIT - high prevents memory and I/O stalls

/NMI - high prevents non-maskable interrupt (doc says always enabled)
/INT - high prevents general purpose interrupt (enabled by EI instruction)

You might want to connect them one at a time to see how it affects the other signals.
Posted on 2004-02-03 04:29:07 by tenkey
The data bus signals look OK to me. The clear LOW's and HIGH's that you see are really correct H or L levels being read or written.
The ramps occur when the bus switches to the high-Z state, that is when the micro is preparing to read something and it tristates its bus, before activating the /READ signal.
If you were to trigger your scope on the /READ or /WRITE signals you would see that the data bus is stable (either LOW or HIGH) when the /RD or /WR signals are active (LOW). I recommend you do this (trigger on the falling edge of these signals) and check the data bus.

/BUSREQ should be HIGH, else the Z80 will release the busses (will tristate them)
/WAIT should be HIGH, or the read/ write cycles will never end
/NMI should be high, else the micro will try to service a non-maskable interrupt, whose routine does not exist
/INT should be high, else the micro tries to service an interrupt, whose routine does not exist

As you can see, all kinds of strange behaviours are possible if these signals are not at the correct levels. Make sure they are correct.
Posted on 2004-02-03 12:07:59 by VVV

I don't like unconnected control inputs, especially with MOS devices.
Connect these inputs to +5V, either directly or with a resistor (anything up to 10k)...

/BUSREQ - high prevents CPU going into 3-state (DMA, inactive) mode
/WAIT - high prevents memory and I/O stalls

/NMI - high prevents non-maskable interrupt (doc says always enabled)
/INT - high prevents general purpose interrupt (enabled by EI instruction)

You might want to connect them one at a time to see how it affects the other signals.

Isn't the NMI and INT inverted logic on the Zilog Z-80, I was going to play with the CPU's I have as well, but school has gotten in the way :( (crap...)

You probably should tie WAIT high, maybe that is what is causing the problem. These guys have jammed into my head the need to connect *ALL* inputs and leave *NO* inputs unconnected!!

Hey Bit7 let me know how everything goes, I was thinking of starting to wire wrap a simple Z80 system with some EPROM, RAM, DAC and some 74LS373's with LED's (indicators). Something I can experiment with.
Posted on 2004-02-03 15:55:30 by x86asm
THANX ALL, it works :)

tenkey, that's right, it was my first problem couse sometime i couldn't see the active low on the IOREQ pin in a OUT tight loop cycle. After pull-upped all that pins, /IOREQ work perfetc.

VVV,
thx, youre the first person that really explain me wat happen in the bus. I was suspecting the Z80 switch to H.I. float state during other operation like between an intruction cycle and other.

Indeed, in the sample i've posted, i couldn't see the /IOREQ go low with my old oscilloscope, becouse the period of a 20msec pause was really great. The /IOREQ low was just a point LOW somewhere that i couldn't even see for trigger and other adjust problems..

So now i'm trying to drive an LCD display of 1 line. I've connected the 8 bit of the data bus to the LCD and i'm having some problem on the initialization. This damned LCDS seems that thay are all following the same HITACHI standard. But seems there are some differences, i've already found different initializations sequences between models.. I've a FORDATA model and i didnt find a complete datasheet of it, only a single sheet on the fordata site.

Anyway thanks again, now bein the Z80 playing :)


B7
Posted on 2004-02-04 01:28:59 by Bit7