Hi all,

I've noticed something strange about the sfence encoding format: "0F AE /7". This instruction takes no arguments, yet the slash indicates a register is expected. My assembler, correctly, created an error when trying to use this instruction. I've looked at the output of my C++ compiler when using sfence and it was "0F AE F8". So I stored that in my instruction encoding table and now it works.

Can anyone confirm this oddity? Is it an error in the Intel documentation or is there really a reason why it's format uses "/7"? Is my 'solution' correct?

Thanks!
Posted on 2004-03-08 02:10:52 by C0D1F1ED
http://www.sandpile.org/ia32/opc_grp.htm (xx111xxx, Group #16)

Look at the map in the link above to see how the instruction fits into the overall scheme. The "/7" is actually specifying the register number portion of the ModRM byte (bits 5-3). This is also indicated in Table A-4 and Table B-16 of the manual.

0F AE F8 is the correct encoding.

The "/7" is Intel's way of saying: We have left a big hole in the encoding here for future expansion.
Posted on 2004-03-08 06:40:08 by bitRAKE
Originally posted by bitRAKE
The "/7" is Intel's way of saying: We have left a big hole in the encoding here for future expansion.

That's what I figured too. But it's strange that they don't specify how to correctly encode the instruction. I haven't completely checked it but apparently anything with ModR/M = 7 is interpreted as sfence. So that doesn't clearly indicate at all that future expansion is possible. The NASM documentation confirms that I have to use F8 but gives no reason for it nor where I could find the official information.

Anyway, I'm already happy it works now. Thanks for the confirmation!
Posted on 2004-03-08 13:21:33 by C0D1F1ED


[...] The NASM documentation confirms that I have to use F8 but gives no reason for it nor where I could find the official information.

Don't forget that one infomation appears in more manual chapters. Open your Intel Instruction Set Reference P4 and read appendix B.6. SSE INSTRUCTION FORMATS AND ENCODINGS, table B-17 and you get the confimation :cool:
These "secondary" chapters are often very interesting, for instance, PIII Intel optimizations manual still documents old FFREEP instruction in appendix C, even through it is not listed in instruction set references since 386.
BTW, this is not a single one hole; what do you think, what instruction uses all encodings between 0F90 /000 and 0F90 /111? The reg/opcode field has no meaning here, since the tttn field can not be encoded in 3 bits, it needs 4 bits. ;)
Posted on 2004-03-09 13:13:43 by MazeGen