Is register ax, bx, dx and cx same in physical aspect?
Is ax faster than bx, dx, or cx?
Posted on 2004-06-08 00:32:00 by bloggs
They are all the same, ax has special short opcodes for some instructions, but they are not faster.
And in realmode, not all registers are entirely equal. bx, si, di, sp, bp are the only ones you can use in address generation, for example. In 32 bit mode, they are all equal.
And some instructions have fixed operands (mul/div/string ops).
Posted on 2004-06-08 02:18:26 by Scali
Besides, none of these registers have "really existed" for a long while - they're aliased onto a pool of internal registers, because of all the register renaming fancyness that makes up for the poor design of x86.
Posted on 2004-06-08 05:11:28 by f0dder
Correction: ...*tries* to make up for... :)
Posted on 2004-06-08 05:31:30 by Scali
Usually, smaller is faster because of memory speed and because it reduces the chance of overcrowding the cahce.
And actually every general register on the x86 has its own unique uses:
EAX: lahf, sahf, cwde, cdq, aaa, aad, daa, das, aam, aad, mul, imul, div, idiv, in, out, salc, one-byte xchg, one-byte ALU with immediate, one-byte move to/from memory, one-byte test with immediate
ECX: loopnz, loopz, loop, jecxz, rep/repnz, repz
EDX: mul, imul, div, idiv, in, out, insb, insd, outsb, outsd
EBX: xlat, , ,
ESP: pushad, popad, push, pop, call, ret, call far, retf, enter, leave, iretd, int, processor exceptions, can't be used as index, no one-byte
EBP: enter, leave, , , , no or addressing modes
ESI: lodsb, lodsd, movsb, movsd, cmpsb, cmpsd, outsb, outsd, , ,
EDI: scasb, scasd, stosb, stosd, movsb, movsd, cmpsb, cmpsd, insb, insd, , ,
Btw, the type of addressing has nothing to do with whether you're in real or protected mode. The default type of addressing is determined when loading a new CS selector in protected mode, and is overridden with opcode 67h. When you go back to real mode, the addressing mode (16-bit or 32-bit) does not change.
Posted on 2004-06-08 10:48:43 by Sephiroth3
Usually, smaller is faster because of memory speed and because it reduces the chance of overcrowding the cahce.


Trace cache defies this completely. There is no relation at all between x86 opcode size and tracecache opcode size.
Also, there are better ways of optimizing for size than choosing the smallest instructions.
And on CPUs without trace cache, the cache is still large enough these days not to worry about code size at all.

And actually every general register on the x86 has its own unique uses


Pretty much all of the instructions you mentioned should be avoided when writing fast code. They are complex and incur decoding stalls or worse.

When you go back to real mode, the addressing mode (16-bit or 32-bit) does not change.


This is a hack known as 'unreal mode'. It is not truly realmode, and does not work on CPUs that only support realmode.
Posted on 2004-06-08 12:16:06 by Scali
confusing!
All of register(ax,bx,cx, ex) is same in physical, or we can not select register actually.
Posted on 2004-06-08 12:59:39 by bloggs
no, ax is not the same that bx and the others that you list.

there are 8 general porpuose registers of 32 bits:

eax, ebx, ecx, edx, esi, edi, esp and ebp.

They also have the proper part in 16-bits, that mean that is the 16 bits from the low part of the above (or the low word) registes of 32-bits.

Only ax, bx, cx and dx of 16-bits can be "splited" in 8-bit registers, in the low and high byte.


For see a posible list see:
http://nasm.sourceforge.net/doc/html/nasmdocb.html#section-B.2.1
The numbers are only encoding for translate the mnemonics to the respective opcode, Dont care much about they now.

Have a nice day or night.

(hint)
8-bits = byte
16-bits = word
32-bits = double word
high or of major significance, are normali the more to the left.
low or of less significance, are normali the more right.
(/hint)
A litttle graph:
(the numbers inside indicate the number of the bit)
[ 31 ][][][][][][][][][][][][][][][ 16 ] [ 15 ][][][][][][][ 8 ] [ 7 ][][][][][][1][ 0 ]
That is a general porpuose register of 32-bits and have a size of a double word.
The low word (marked with red) is the 16-bit register and have a size of a word.
This low word have a high byte(italic face) and a low byte(bold face) each of this parts is a 8-bit register and have a size of a byte.

Like you see:

eax -> ax -> ah & al.
ebx -> bx -> bh & bl.
edx -> dx -> dh & dl.
ecx -> cx -> ch & cl.

Posted on 2004-06-08 18:06:14 by rea
esp isn't exactly general-purpose ;)
Posted on 2004-06-08 18:24:37 by f0dder
esp - general purpose. code 100
Posted on 2004-06-08 18:29:38 by The Svin
from an opcode sense... but not "in the real world".
Posted on 2004-06-08 20:03:46 by f0dder
mmm, is because is for stack operations, where are some instructions that are register specific and the result cant be changed from register, is the same with esp.

The problem is that the operations that involve the general porpuose register esp are directly related to, reentrant code, local scope of memory.

Where you can still use eax for other things diferent that multiply, if you use esp for other things, you "sacrificate" have local variables, even call a simple function in other part of memory, exept that you write completely a plain executable, where you can use esp like any other registry, you still can use esp and ebp at the same time, with the need to save them in memory of the executable, but at the end, you will need the 'hability' of the stack to grow and be used like is or restore the values. If you need two more registers in your proc and you can add some extra space in the static 'data' memory of the executable, you can still get that 2 extra registers from ebp and esp, where you need to restore them in order to pass arguments and call.


Have a nice day or night.
Posted on 2004-06-09 12:29:12 by rea