When scaling is not used in 32bit addressing mode, it is not obvious which of the two addressing registers is coded as Base and which one is Index. Intel gives no recommendation in IA-32 Manuals and here is the outcome:
some products (MASM, RosASM, The Svin's Modrm1op) assemble
MOV EAX, as
8B 44 1D 00 (i.e. index=EBX, base=EBP, selector=SS)
while other products (TASM, NASM, FASM, HIEW, OllyDbg) will dis/assemble this as
8B 04 2B (i.e. base=EBX, index=EBP, selector=DS).
Which version do you prefere, should the former (left side) register be coded as Index or Base?
some products (MASM, RosASM, The Svin's Modrm1op) assemble
MOV EAX, as
8B 44 1D 00 (i.e. index=EBX, base=EBP, selector=SS)
while other products (TASM, NASM, FASM, HIEW, OllyDbg) will dis/assemble this as
8B 04 2B (i.e. base=EBX, index=EBP, selector=DS).
Which version do you prefere, should the former (left side) register be coded as Index or Base?
I see interpreting left register as base is more convenient. In 32 bit world it doesn't matter though (EBP & EBX point to the same address).
I can override the base/index interpretation by using .
I can override the base/index interpretation by using .
If it is a macro assembler the default should be the smallest encoding, and this is simply because a macro assembler does not allow a 1-to-1 translation to opcodes if registers are passed as parameters and abstractions are simplified internally. It is just much harder to control.
Otherwise, allow the selection through abstraction and state the default used. All current processor manuals state to use the smaller encoding.
Otherwise, allow the selection through abstraction and state the default used. All current processor manuals state to use the smaller encoding.
Sorry...
I mean DS & SS registers point to the same addr (not EBX & EBP) :)
I mean DS & SS registers point to the same addr (not EBX & EBP) :)
We know what you meant :tongue:
And I know that you knew ;)
MOV EAX, and MOV EAX, are different instructions so I cannot abstract and use the same opcode, as bitRAKE suggests.
Of course, we all know that SS and DS are the same selectors in flat memory model, but the assembler doesn't.
Of course, we all know that SS and DS are the same selectors in flat memory model, but the assembler doesn't.
Of course, we all know that SS and DS are the same selectors in flat memory model, but the assembler doesn't
I think you mean base of segment, not selectors.
In ring 0 you need to have SS with DPL 0, thus though in Win32 in both ring3 and ring0 descriptors in SS has 0 base, the descriptors for SS in ring3 and ring0 are different. It's not 'cause of something related to Win32, but to protect mode of x86 - if your CS has DPL 0 then SS should also point to descriptor with DPL 0.