hi to all, just have simple question on uprocessor design.
assume i add to processor (say i have 8051) a ram on it full capacity, 64k, and a rom 64k too. i dont have any problem routing the addr and data busses and the control signal. but, i still dont have clue how to address i/o devices through addr busses. is it so called memory mapped i/o or i just missed it?

thanks
Posted on 2004-08-24 20:55:53 by dion
It depends on the processor. Check the data sheets for I/O signals.

For example, there are no special I/O instructions in the 8051. For that processor, you must use the special function registers (and dedicated I/O pins), or memory mapped I/O.

In contrast, the Z80 has an IOREQ signal that is active when you execute an IN or OUT type of instruction. You also have the option of using memory mapped I/O on this processor.

If you use memory mapped I/O, a full install of RAM and ROM will conflict with input data. You will need to disable some portion of your memory to allow memory mapped input.
Posted on 2004-08-25 00:20:43 by tenkey
If you use memory mapped I/O, a full install of RAM and ROM will conflict with input data. You will need to disable some portion of your memory to allow memory mapped input.


yes, i use full install of 64k ram and 64k rom. i know that i should/must use ram address portion instead of rom address, to be reserved for some i/o devices.

i have just think to do it, i must first, decode all the addr bus, to the i want, i.e addr 0010h for register x1, 0011h for register x2, and soon, depend on the device's register addr.

now, that i had decode all the addr bus, i must also include the read/write signal, so it only effect to ram addr, not rom addr. rom addr uses /PSEN in my case (8051 family).

but this solution was so over, because every for every device addr, i need another chip to decode the addr, what a wasteful design, i though.
how exactly to implement memory mapped i/o?
Posted on 2004-08-25 01:04:04 by dion
Try 80L188EB. It's got all that you need and programs same instruction set as 8088 like DOS. It is surface mount though but when I did first design with one I bent one pin up and one down and soldered strap wire to the pins than apoxied them in place. That's if you don't have a table top router or a cheap method to make a PCB for it.
Posted on 2004-08-25 13:02:00 by mrgone
You can use A15 from the processor to enable or disable a RAM chip. This makes A15 your MEM/IO signal. If 32K is too much to lose, you can AND A15 and A14 for a 16K I/O space. For a smaller I/O space (and less RAM loss), more address bits need to be ANDed together.

Within the I/O space, you can divide it further with a decoder. The 3-to-8 decoder is popular. You can keep parts count low by partial decoding. In partial decoding, you don't use all the address bits. The unused bits are "don't care" bits.
Posted on 2004-08-25 16:18:29 by tenkey
ok, thanks for helpful reply guys :)
Posted on 2004-08-26 20:48:24 by dion