Hi all,

I am still bizy whit my OS, and i implemented real paging into the system, so by using 4MB and 4KB pages.
Before this i only used 4MB pages, those where paged directly to phisicial memory, so Phisical and virtual memory where the same.

but sinds i implemented the new paging method i got a nasty bug in my system, look at this example:

Offset             data inside

Some data:                                                      ; this the Paged section of memory, so virtual
0x80019000: 00,45,AB,00,  00,00,00,00
0x80019008: 00,00,00,00,  5F,55,00,00

4KB Page Table, for 0x8000.0000:                      ; this is phisical memory
0x00802060: 008FF067   ,00901067                   ; <------ Paged to 8F.F000 and 90.0000, Present/User/RW   bit's
0x00802068: 8D001006   ,8D001006                  ; <------ dont exist yet. Present bit == 0

Some data, which should be the same as, 0x80019000h:           ; this is phisical memory
0x00901000: 00,00,00,00, 00,00,00,00              ; see page table offset 00802064
0x00901008: 00,00,00,00, 00,00,00,00

As u can see is the data at offset 0x80019000, completely different from the data at 0x00901000.
But how is this possible, could it be related whit wrong cache usage, or what else could go wrong whit paging.

Posted on 2006-01-10 13:55:15 by pyr0_mathic
At what address does that particular PTE start? Also, what does the corresponding PDE/CR3 have at that instant?
Posted on 2006-01-10 14:25:45 by SpooK
lo, thx for the quick reply.

The PDE entry for offset 0x8000.0000 or 0x80019000, is following: 0x00802027 (so present/RW/User bits) + accessed bit is set
so PTE starts at 0x00802000.

Whit content:      ; offset 0x80019000, PTE inside 0x00802000:  0x19 th, so 19h * 4 = 64h, so: 0x00802064
0x00802000: ....
0x00802060: 008FF067   ,00901067        ; <------ Paged to 8F.F000 and 90.0000, Present/User/RW   bit's
0x00802068: 8D001006   ,8D001006       ; <------ dont exist yet. Present bit == 0

This is the PDE-entry for offset 0x00901000, 0x008000E7 (so present/RW/User bits) + 4MByte bit is set + Accessed/Dirty
Data offset == 0x00800000

Regards PyroMathic
Posted on 2006-01-10 14:48:14 by pyr0_mathic
lo, i tried out a couple of more things

I now Reload CR3 after every write to a PTE, so:
mov eax,cr3
mov cr3,eax

i also used added "WBINVD", so Write back all Cache and invalidate the cache, internal/external. but this only makes the computer slower (a lot...), doesnt change a thing.

i also tried to implement "INVLPG", i just cant find a good description in the intel docs on what the first operator must, so:
INVLPG m            ; m, "is a memory location", but is it the location of the PTE,
                          ;                        or the content of the PTE or phisical addr of the page...

i also made the segment 0x0090.0000 - 0x0100.0000, reserved (so it wouldnt be allocated by, my MemAlloc proc), but then i got the same error as above, only then whit an other phisical address and other content in it.

State of CR3:
CR3 == 0x0000.1018                ; so PCD/PWT are set resulting in: dont Cashe PageDirectory + Write through enabled.

I got a intel Pentium 3, compac

Regards PyroMathic
Posted on 2006-01-11 09:46:11 by pyr0_mathic
If you need immediate help, check out this forum. I won't be able to analyze your problem anytime soon (too in-depth and ambiguous for intuitive troubleshooting purposes and I am strapped for time).
Posted on 2006-01-11 11:25:36 by SpooK

the m is the linear address of the page which is to be invalidated.
Posted on 2006-01-11 12:58:33 by japheth
Thx, for the replies.

Am still looking inside the forum, seems to have lots of thingis about os-building.

Regards PyroMathic.
Posted on 2006-01-11 13:12:03 by pyr0_mathic
lo, again...

problem is solved, cause was: i used the wrong code to enable the A20 line :S.... but now it works, so i can continue building my OS.

1 positive thing about this, now i atleast understand how to use the cashe, MTRRs, etc....

Posted on 2006-01-12 06:46:51 by pyr0_mathic