Hey guys .

I would love if someone here could explain to me or anyone else who reads this thread about what happens when i do the following.

MOV EAX, 30
MOV EBX, EAX
MOV my_var1, EAX
MOV DWORD PTR my_var, EAX

Like for example.

Mov eax,30 how would that work? what buses are used etc.
Or if you can point me to a nice explanation I would appreciate that very much.

Trying to get a good understanding of what happens with the hardware side of things.

Thank alot.

;)
Posted on 2006-06-07 16:33:58 by gavin_
gavin_ ,



Mov eax,30 how would that work? what buses are used



This will only be the basics, something you will understand and
not all the hardware details, just the basic's

When that intruction is executed the CPU puts out on the address
lines the address to where that DWORD is, and also puts out on the
control lines a Read, this on some CPU's could be a R/W line. But I will not
really go into that.

The DWORD is then transfered along the data lines to the CPU.
and latched into the eax reg.

The above is just the basic's as there are alot more things in todays
CPU and memory hardware that take place, but it is the basics.

Mind you all this takes place during the execute state
the CPU goes through 3 state, Fetch, Decode, Execute.


Zcoder....

Posted on 2006-06-07 17:08:33 by Zcoder
Do you want to know how it actually works, or do you want to know the simplest way that could work?

There is a mismatch between instruction execution and memory access in the high performance processors used in modern PC's, due to caching.

We could start with the simplest model where each instruction byte is fetched, one at a time, followed by the execution phases when data is read from or written to memory.

Then we could advance to instruction caching, where bytes from code memory are fetched several (8 on a Pentium) bytes in a single bus cycle, and where the processor has the option of fetching instructions from either the cache or from memory.

After that, we could include data caching, which adds the option of caching on write operations.

Caching reduces the number of times memory is accessed.

And then after that, we could add the address translation created by the segmentation and paging hardware. This last subject is covered in the wiki book.
Posted on 2006-06-08 01:01:31 by tenkey
Zcoder....

Thats a good way you explained that and I have started to read the basics I will come back to this thread later on when I have more time to read.

tenkey

I'm just doing some more reading before I answer your post.
Thanks alot lads.

Posted on 2006-06-11 10:04:34 by gavin_