detecting SSE1-SSE3 is no problem but does someone know how to detect official (no hack!) if SSE4 is available or not? Here is my code for detecing SSE3 seems to work without any problems.

  PUSH Ebx
  MOV    Eax, 0x80000001
  cpuid                       
  MOV    Eax, Edx           
  SHR    Eax, 31           
  AND    Eax, 1   
  POP Ebx
Posted on 2006-08-19 17:20:03 by Ralf
If you can detect Core 2, you can detect sse4.
Posted on 2006-08-21 12:20:41 by MazeGen
How about setting up a SEH, and executing an example opcode or sequence of opcodes?
If you get an exception, your code will then configure itself:

.data
  HasSSE4 dd 0
.code

.prepFatal  ; a macro to start SEH
    ; do some SSE4 code
    ;...
    mov HasSSE4,1
.doFatal ; on exception
    ;mov HasSSE4,0
.endFatal


Isn't this a much cleaner way :) ? (no way to make a wrong judgement on the availability of the extended instruction-set on AMD, Intel, and other cpus if any ever join the x86 domain).
Posted on 2006-08-21 13:55:36 by Ultrano
Humm, the "detecting core2" might miss out on other CPUs that end up supporting SSE4...

and the SEH way might trigger some other instruction on one of the "fringe" x86 CPUs (not very likely though, but it *is* a possibility).

Doesn't intel have anything to say on the matter?
Posted on 2006-08-21 13:59:49 by f0dder
You'd think by now, someone would compile a library for detecting the various hardware available today....

Regards,
:NaN:
Posted on 2006-08-21 14:08:31 by NaN
I think Agner had something of the sort in his optimization material site, not absolutely sure though.
Posted on 2006-08-21 18:08:40 by SpooK

and the SEH way might trigger some other instruction on one of the "fringe" x86 CPUs (not very likely though, but it *is* a possibility).

:( what other x86 cpus are there? I'd like to research a bit on this, because I favor the SEH approach (although I haven't used it in commercial apps yet... needn't optimize with SSE).

The sourcecode of an app, called PCSX2 has some cpu detection routines in x86\ix86\ix86_cpudetect.c . (I'm not sure about infringing the rules of the board with this url, since this is an emulator , pls remove the url if I'm doing so.)
Posted on 2006-08-21 18:35:40 by Ultrano
Humm, I don't think linking to an emulator is a problem - can't see why it would be, as long as it's not a "click here to download rom warez omfg" :)

Other x86 CPUs? VIA C3, which has built-in AES/Rijndael routines using the SSE units... haven't studied how it does this, but it requires a couple opcodes afaik.

Then there's the transmeta, but I don't think they have special x86 instructions?
Posted on 2006-08-21 18:37:51 by f0dder
I don't see any problem. Not allowing people to download legally written software, like an emulator, just because of related material... is like shunning people for downloading Adobe Acrobat because you are afraid they will obtain illegal copies of books/docs.

If I see an increase in the unwanted/illegal TO wanted/legal ratio, related to a subject like our issues with RE requests... which illustrate overwhelming intention to do something illegal... is when it is time to throttle back and shoot people down ;)

So far, I haven't seen any massive "0MFG wh3r3 4r3 t3h r0mz!!11!1" requests yet... so you have a green light :)
Posted on 2006-08-21 19:22:46 by SpooK
CPUID.01H:EDX.MMX 
CPUID.01H:EDX.SSE 
CPUID.01H:EDX.SSE2
CPUID.01H:ECX.SSE3
CPUID.01H:ECX.SSE4

CPUID.80000001H:EDX.3DNow! 
CPUID.80000001H:EDX.E3DNow!
Posted on 2006-08-22 01:21:23 by Nexo

I think Agner had something of the sort in his optimization material site, not absolutely sure though.


http://www.agner.org/optimize/#asmlib

InstructionSet function; it seems detecting SSE4 is still unsupported.
Posted on 2006-08-22 02:30:28 by MazeGen
Well, if Nexo is right and this will be true for other CPUs, problem is solved :)

Btw, is the intel documentation for core2/SSE4 even ready yet? Agner writes that he got hold of preliminary info/whatever.
Posted on 2006-08-22 07:46:37 by f0dder
The latest revision (20) is just Core 1. SSE4 instructions are mentioned only in opcode map, there is no description of them.
Posted on 2006-08-22 07:50:36 by MazeGen