I have a question about linear address.
This is first picture:

This is the second picture:

I confused here.

1-)Segmantation without paging:

a) Linear address is sum of base address and offset and equals to physical address.
Linear address = base address + offset = physical address
b)  ... where base address + offset points to.
Linear address = *(base address + offset) = physical address

2-) Segmantation with Paging

a) Linear address = base address + offset
b) Linear address = *(base address + offset)

The first picture shows addition like pointer. But the second addition shows address directly.
I hope i can explain.

Which one is true?
Posted on 2007-09-09 14:24:27 by sawer
The bottom picture shows the first step in the x86 address translation mechanism, which is segmentation. Paging is a translation mechanism that is added on top of (performed *after*) segmentation, as illustrated in the first picture. Even the newest x64 processors still require basic segmentation (a valid GDT) to operate even though segmentation is nearly deprecated in long mode.

There is a catch-22, that makes it seem like the other way around, in that if Paging is enabled... your GDT and the like must be at the correct *Virtual* (paging) address for that initial part of the translation. This is because even the segmentation mechanism must resolve its own addresses through paging before it completes the address translation request and passes it on to the paging mechanism itself. Page Directory and Page Tables entries, including the PDBR/CR3, are the only addresses that reflect physical memory in the paging mechanism, everything else before that is virtual.

It takes a bit to get used to, but I tend to think of Segmentation as a "magnifying glass" pointing at a specific part of memory while I think of Paging as table of virtual memory to physical memory pointers... much like "change of address" intercepts at your local post office.
Posted on 2007-09-09 17:11:44 by SpooK
Thank you Spook for this answer.
I am very sorry But i could not follow what you mean.
Could you please tell me the correct answer, more simplify.

Thanks again.
Posted on 2007-09-09 17:57:59 by sawer

I am very sorry But i could not follow what you mean.

That about sums up understanding these mechanisms altogether. There is a breaking point at which you fully understand these things... but until then, the process can be frustrating... just stick with it.

This explanation assumes you are operating in 32-bit Protected Mode of an x86 processor.

  • A Logical Address is the numerical address *before* any translation mechanisms occur.

  • A Linear Address represents a address within the full address space in which the translation is performed, but may not represent a 1:1 correlation to Physical Address (e.g. RAM) space. When paging is disabled, Linear Address Space has a 1:1 correlation to Physical Address Space... what you see is what you get. When Paging is enabled, Linear Addresses turn into Virtual Addresses.

  • A Virtual Address is an address that has been translated by the Segmentation mechanism and is ready to be translated by the Paging mechanism.

  • A Physical Address is one that finally goes beyond the CPU and truly reflects the use of the Address, Control and Data BUS lines to whatever device is being accessed... with the most common access directed towards RAM.

Translation Path
  • Logical Address (Offset) + Base of Segment (Segment Register/GDT/LDT) = Linear Address.

  • If paging is disabled, Linear Address = Physical Address... end of the line.

  • If paging is enabled, Linear Address = Virtual Address; Then that Virtual Address is translated to a Physical Address... end of the line.

Posted on 2007-09-09 19:21:55 by SpooK
Hmm, now OK.
Thank you very much for this explanation SpooK.

Good works...
Posted on 2007-09-10 00:17:43 by sawer