Hi
We know that data travels between the CPU and memory on parallel wires called a bus.
For example this code send signal to memory(ram).
But for IN\OUT instructions, where does the data travel?
This is for step motor:
Where is 001b going? I don't think that there is a wire between step motor and CPU. Am i wrong?
I am trying to find some schemas about 8086 and its ports. I can't find anything.
Any help(link or comments) to understand IN/OUT internals will be appreciated.
Thanks
We know that data travels between the CPU and memory on parallel wires called a bus.
For example this code send signal to memory(ram).
MOV BX, 15Eh ; set BX to 15Eh.
MOV , CX ; copy contents of CX to memory at B800:015E
But for IN\OUT instructions, where does the data travel?
This is for step motor:
MOV AL, 001b ; initialize.
OUT 7, AL
Where is 001b going? I don't think that there is a wire between step motor and CPU. Am i wrong?
I am trying to find some schemas about 8086 and its ports. I can't find anything.
Any help(link or comments) to understand IN/OUT internals will be appreciated.
Thanks
I/O information travels on the very same data and address buss.
However one of the control buss signals will "signal" that this is an I/O address space WR/RD cycle as opposed to a memory address space RD/WR cycle.
Alternatively the device could be memory mapped and then it behaves exactly like a RAM address ( but slightly slower).
This address will be detected or decoded electronically by an attached device (CS gets activated) and that device only will get or provide the values.
Then this additional device might have another electronic interface (Open Colector, IC2, optoelectronic or or simply power amplified and protected) that will drive the motor or relay or yet another device.
Get to study electronics... more exactly digital electronics. University 3rd year if I recall correctly :P
Alternatively search books on digital electronics. Decoders, latches, buffers, counters, busses (standard, PCI, etc). You need to know the basics of gates and J-K, R-S and D flip flops and ROM/RAM memory selection (CS, WR, RD, EN, RAS, CAS)
There is an address buss, and data buss (often on the same wires for economy) and an Control buss.
Things get slightly more complicated in today practice since you have the PCI bus and the south bridge to deal with (or JTAG on embeded).
And it COULD be an wire in between you CPU and the device if the power requirements are very low and your CPU is an SOC.
However one of the control buss signals will "signal" that this is an I/O address space WR/RD cycle as opposed to a memory address space RD/WR cycle.
Alternatively the device could be memory mapped and then it behaves exactly like a RAM address ( but slightly slower).
This address will be detected or decoded electronically by an attached device (CS gets activated) and that device only will get or provide the values.
Then this additional device might have another electronic interface (Open Colector, IC2, optoelectronic or or simply power amplified and protected) that will drive the motor or relay or yet another device.
Get to study electronics... more exactly digital electronics. University 3rd year if I recall correctly :P
Alternatively search books on digital electronics. Decoders, latches, buffers, counters, busses (standard, PCI, etc). You need to know the basics of gates and J-K, R-S and D flip flops and ROM/RAM memory selection (CS, WR, RD, EN, RAS, CAS)
There is an address buss, and data buss (often on the same wires for economy) and an Control buss.
Things get slightly more complicated in today practice since you have the PCI bus and the south bridge to deal with (or JTAG on embeded).
And it COULD be an wire in between you CPU and the device if the power requirements are very low and your CPU is an SOC.
Thank you BogdanOntanu.
Also, I think this article( http://babbage.cs.qc.edu/courses/cs343/UART/ ) what i looked for...
Also, I think this article( http://babbage.cs.qc.edu/courses/cs343/UART/ ) what i looked for...
Yeah, well, THAT article talks about a rather old device and in an general and not very detailed mode.
But it can be a starting point.
It gives you no ideea about how device are selected and how internal device ports are selected and no internal schematics of the device (other than a faint block diagram)
Oh... and it does not show the FSM schematics or states.
And where is the talk about device FSM? FSM's do play a crucial role in digital electronics (together with combinational logic).
The good part is that the UART device is still present in modern chip sets... well almost. Hence you could do some hands on "old style driver" programming and hardware I/O port access.
But it is programming NOT electronics nor Chip Select information. It does not talk about the pins where Tx and Rx are exposed, about the voltage levels and about other important control signals like CTS and RTS and DTR... unless it is XON/XOFF protocol.
But it can be a starting point.
It gives you no ideea about how device are selected and how internal device ports are selected and no internal schematics of the device (other than a faint block diagram)
Oh... and it does not show the FSM schematics or states.
And where is the talk about device FSM? FSM's do play a crucial role in digital electronics (together with combinational logic).
The good part is that the UART device is still present in modern chip sets... well almost. Hence you could do some hands on "old style driver" programming and hardware I/O port access.
But it is programming NOT electronics nor Chip Select information. It does not talk about the pins where Tx and Rx are exposed, about the voltage levels and about other important control signals like CTS and RTS and DTR... unless it is XON/XOFF protocol.