Hi
I searched for interrupts and find some informations that conflicts..

The first one:
Interrupts:
1) Reset: caused by change in voltage on RESET input pin
2) Internal interrupts: caused by executing certain non-flow control
instructions.
3) Software interrupts: caused by executing INT instruction.
4) Non-maskable interrupt: Caused by change in voltage on the NMI pin.
5) External hardware interrupts: Caused by change in voltage on the INTR pin
The order of the five interrupt classed listed above is the same as their priority order.
Reset has the highest priority and external hardware interrupts the lowest.


The second one:
Lower interrupt vectors have higher priority
Lower priority canít interrupt higher priority
Higher priority can interrupt lower priority
ISR for INT 21h is running
Computer gets request from device attached to IRQ8 (INT 78h)
INT 21h procedure must finish before IRQ8 device can be serviced
ISR for INT 21h is running
Computer gets request from Timer 0 IRQ0 (INT 8h)
Code for INT 21h gets interrupted, ISR for timer runs immediately, INT21h finishes afterwards


Which one is true?

Is software interrupts(INT) priority higher than external hardware interrupt(IRQ) or vice versa?
Thanks...
Posted on 2008-03-04 18:07:09 by sawer
Second one sounds wrong to me, but I'd have to look through the intel manuals to be able to answer with certainty. It also depends on the running OS, as that might block out interrupts under certain situations.
Posted on 2008-03-04 18:59:47 by f0dder
One more source:

1-)divide error interrupt, INT n, INT0                    highest
2-)NMI
3-)INTR
4-)TRAP flag                                                  (single step) lowest


And The IA-32 Intel(R) Architecture Software Developer's Manual Volume 3_ System Programming Guide:

Table 5-2. Priority Among Simultaneous Exceptions and Interrupts
Priority Description
1 (Highest) Hardware Reset and Machine Checks
- RESET
- Machine Check

2 Trap on Task Switch
- T flag in TSS is set

3 External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT

4 Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)

5 Nonmaskable Interrupts (NMI)

6 Maskable Hardware Interrupts

7 Code Breakpoint Fault

8 Faults from Fetching Next Instruction
- Code-Segment Limit Violation
- Code Page Fault

9 Faults from Decoding the Next Instruction
- Instruction length > 15 bytes
- Invalid Opcode
- Coprocessor Not Available

10 (Lowest) Faults on Executing an Instruction
- Overflow
- Bound error
- Invalid TSS
- Segment Not Present
- Stack fault
- General Protection
- Data Page Fault
- Alignment Check
- x87 FPU Floating-point exception
- SIMD floating-point exception


I don't understand why all of them are different.
Posted on 2008-03-05 10:55:22 by sawer
I don't understand why all of them are different.
Probably because they were written at different points in time, or by people who thought they knew but didn't quiteTM :) - I'd trust the intel manual.
Posted on 2008-03-05 11:03:54 by f0dder

I don't understand why all of them are different.
Probably because they were written at different points in time, or by people who thought they knew but didn't quiteTM :) - I'd trust the intel manual.


Agreed. The Intel version is showing some thought in how you'd want to opt for system stability with such interrupt priorities.
Posted on 2008-03-05 21:51:20 by SpooK