My question is how we can write effective address in 16, 32 or 64 bit modes. We know that the following is a valid effective address in 16 bit IA-32 protected:

+disp8

Can we specify: +disp8 as an address?

Also suppose we write a code for IA-32 protected, the following is a valid effective address:

+disp32

But is , +disp32 a valid valid effective address? how about +disp32?

In real mode(16-bit) we have +disp8 but is "+disp8" valid?

And my last question is that how you write a valid address in 64 bit mode?

+disp8

Can we specify: +disp8 as an address?

Also suppose we write a code for IA-32 protected, the following is a valid effective address:

+disp32

But is , +disp32 a valid valid effective address? how about +disp32?

In real mode(16-bit) we have +disp8 but is "+disp8" valid?

And my last question is that how you write a valid address in 64 bit mode?

Short answer: no. No "partial registers" are allowed in any size, that I'm aware of. A 16-bit EA consists of an optional displacement/offset, an optional base register (bx or bp), and an optional index register (si or di). A 32-bit EA consists of an optional displacement/offset, an optional base register (any 32-bit register), an optional index register (any 32-bit register but esp), and an optional scale (1, 2, 4, or 8). You're on your own with 64-bit, but I think it's the same as 32-bit(?).

Best,

Frank

Best,

Frank

"Intel 64 and IA-32 Architecture Software Developer's Manual", Volume 1, Chapter 3.7.5:

Every address consists of:

- A displacement

- A base

- An Index

- A Scale

Where:

A displacement is a 8-, 16-, or 32-bit value, in either 32-bit or 64-bit mode.

A base is a value stored in a 16-bit general-purpose register in 16-bit mode, a 32-bit reigster in 32-bit mode, and a 32-, or 64-bit GP register in 64-bit mode.

An Index is a value stored in a general-purpose register (with same rules as above), excluding SP/ESP/RSP which can't be used as an Index in any mode.

A Scale is a constant value of 1, 2, 4, or 8, in either mode.

The resulting effetive address has the following formula: BASE + INDEX*SCALE + DISPLACEMENT

Any of the above components can be omitted, but at least one must be present and if there is only one, it must not be the Scale component.

Additionally, 64-bit mode offerst one, unique addressing mode, caled "RIP-relative addressing" which has the following formula: RIP + DISPLACEMENT, where RIP is the value of RIP register and Displacement is a 32-bit value.

All calculations on values in each component are SIGNED, so it is possible to place negative numbers in them (except in the Scale, of course) and effectively subtract a value from the effective address, instead of adding it.

Every address consists of:

- A displacement

- A base

- An Index

- A Scale

Where:

A displacement is a 8-, 16-, or 32-bit value, in either 32-bit or 64-bit mode.

A base is a value stored in a 16-bit general-purpose register in 16-bit mode, a 32-bit reigster in 32-bit mode, and a 32-, or 64-bit GP register in 64-bit mode.

An Index is a value stored in a general-purpose register (with same rules as above), excluding SP/ESP/RSP which can't be used as an Index in any mode.

A Scale is a constant value of 1, 2, 4, or 8, in either mode.

The resulting effetive address has the following formula: BASE + INDEX*SCALE + DISPLACEMENT

Any of the above components can be omitted, but at least one must be present and if there is only one, it must not be the Scale component.

Additionally, 64-bit mode offerst one, unique addressing mode, caled "RIP-relative addressing" which has the following formula: RIP + DISPLACEMENT, where RIP is the value of RIP register and Displacement is a 32-bit value.

All calculations on values in each component are SIGNED, so it is possible to place negative numbers in them (except in the Scale, of course) and effectively subtract a value from the effective address, instead of adding it.

thank you for the replies, both Frank and ti_mo_n. You are right , we have restrictions, in 16 bits mode, only BX or BP can be base registers as well as SI or DI as index registers and in 32 and 64 bits we can not specify ESP(and RSP) as index registers.

In 64 bits we can use the same addressing modes of 32 bits but if REX.W=1, 64 bits base and index registers can be used(I mean CPU decodes the instruction format considering 64 bits registers)

In 64 bits we can use the same addressing modes of 32 bits but if REX.W=1, 64 bits base and index registers can be used(I mean CPU decodes the instruction format considering 64 bits registers)