How CPU recognizes the RAM size?
Posted on 2010-05-18 00:34:32 by logicman112
logicman112,

Short answer: it doesn't.

Memory module (modern one) contains EEPROM chip, named SPD, which can be accessed via SMBus, usually implemented by south bridge. During POST BIOS reads EEPROM contents, programs memory controller appropriately and builds memory map which is then made available via int 15h/E820h or similar APIs (E801h, E881h).
Posted on 2010-05-18 15:41:31 by baldr
thank you very much for the reply.
So CPU reads the EEPROM at SMBUS address space? or the south bridge or memory controller?!!
Posted on 2010-05-19 00:28:10 by logicman112
logicman112,

Again: CPU doesn't. Programs do (usually BIOS). There is no specific MSR/CR/whatever in CPU that is related to the whole SMBus/SPD business.

South bridge implements SMBus host controller as one of its functions. BIOS uses this host controller to communicate with SPD in order to read corresponding memory module parameters, and programs memory controller of north bridge according to them during POST.

There are several programs that can access SPD and show its contents, either raw or cooked.

P.S. You may wonder why I'm so obsessed with that "CPU doesn't" thing. Well, at low level it's important to know exactly who and how does what. And who doesn't. ;-)
Posted on 2010-05-19 01:01:33 by baldr
baldr: how much does the story change for CPUs with embedded memory controller?
Posted on 2010-05-19 06:12:35 by f0dder
SPD is read via SMbus (usually an I2C variant). No need for controllers.


South bridge implements SMBus host controller as one of its functions. BIOS uses this host controller to communicate with SPD in order to read corresponding memory module parameters, and programs memory controller of north bridge according to them during POST.

Yeah, people usually don't appreciate all the hard work the south bridge does during POST ^^
Posted on 2010-05-19 14:31:13 by ti_mo_n
how much does the story change for CPUs with embedded memory controller?


Not a much as I expect. Do you think in that case CPU reads SPD/configures memory controller by itself? Intel Core i7-900 (the one I've read datasheet for) doesn't seem to have SCL/SDA pins for such interaction; I'm not into Core iX/AMD64 business yet, so it's just my speculations. ;-)
Posted on 2010-05-20 15:48:36 by baldr