Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 1:  Basic Architecture

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3.3.7 Address Calculations in 64-Bit Mode
All 16-bit and 32-bit address calculations are zero-extended in IA-32e mode to form
64-bit addresses.

3.4.1.1 General-Purpose Registers in 64-Bit Mode
If the result of an 8-bit or 16-bit operation is intended for 64-bit address calculation, explicitly sign-extend the register to the full 64-bits.
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Some lines at 3.4.1.1 seems wrong or contradicts 3.3.7 as follows:

At 3.4.1.1: ...If the result of an 8-bit or 16-bit operation is intended
for 64-bit address calculation, explicitly sign-extend the register to the full
64-bits......
How we can have 8/16 bits operation in Intel 64-bits mode? Can displacement be 8 or 16 bits in Intel 64-bits mode? Because the registers(in indirect memory addressing) can not be! The other possibility is that this sentence is for compatibility mode, in that case how we have always sign-extension!! (means zero-extension, at 3.3.7, is wrong!!)

PS. registers can be 8 or 16 bits in Intel 64 but they are not used to address memory! When it is said that the result of the registers are used in address calculation, means these registers are used in indirect memory addressing. But we have restriction choosing registers in indirect memory addressing and in Intel 64, we can not choose BL or BX as a pointer to memory. Because it talks about 8-bit and 16-bit operands, these operands may be 8 or 16 displacements then. But can we specify  16 bits displacements in Intel 64?






Posted on 2010-06-07 00:22:50 by logicman112
logicman112,

Clause from 3.4.1.1 isn't about using 8/16-bit registers in EA calculation, it only emphasizes the fact that if you're using 8/16-bit instruction (mov al, 1), the rest of the register is not cleared (as in case of mov eax, 1). Whether you should do signed or unsigned extension, depends on the kind of value in partial register (if you suppose to use full register in EA calculations).

3.3.7 subchapter probably should refer to compatibility submode instead of 64-bit submode where latter isn't applicable.
Posted on 2010-06-07 02:50:20 by baldr
Thank you baldr.
if CPU fetches an instruction from a 16 bit code segment and the instruction uses address size override prefix (67H):
MOV  , 87 

Does it use the content of EBX as a pointer or BX?
Posted on 2010-06-07 21:37:23 by logicman112
3.3.7 subchapter probably should refer to compatibility submode instead of 64-bit submode where latter isn't applicable.


Another case is Intel 64 instruction with address size override prefix I think.
Posted on 2010-06-07 22:17:05 by logicman112

if CPU fetches an instruction from a 16 bit code segment and the instruction uses address size override prefix (67H):
MOV  , 87   

Does it use the content of EBX as a pointer or BX?


On the low level there are no mnemonics. Are you talking about 67 c7 07 57 byte sequence? While c7 07 57 is a mov byte, 87 16-bit instruction, with prefix it is decoded as mov byte, 87 (ModR/M encodings in 16- and 32-bit code are quite different).
Posted on 2010-06-08 00:18:05 by baldr
Intel manual:

3.3.7 Address Calculations in 64-Bit Mode
In 64-bit mode, the effective address components are added and the effective address is truncated (See for example the instruction LEA) before adding the full 64-bit segment base.
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I think the manual talks about 67H when we override default address size.

On the low level there are no mnemonics. Are you talking about 67 c7 07 57 byte sequence? While c7 07 57 is a mov byte, 87 16-bit instruction, with prefix it is decoded as mov byte, 87 (ModR/M encodings in 16- and 32-bit code are quite different).


As your words indicate , when we override the address size, our addressing mode changes. Then If we use 67H (in 64 bits) we will change the address size to 32 and base and index registers will be 32 bits. Why Intel manual says it should be truncated?!
Truncation means we consider 64 bits registers and then consider the lower 32 bits.



Posted on 2010-06-12 22:16:46 by logicman112

Displacements and Immediates. Generally, displacement and immediate values in 64-bit mode are not extended to 64 bits. They are still limited to 32 bits and are sign extended during effective-address calculations. In 64-bit mode, however, support is provided for some 64-bit displacement and immediate forms of the MOV instruction.

Zero Extending 16-Bit and 32-Bit Addresses. All 16-bit and 32-bit address calculations are zero- extended in long mode to form 64-bit addresses. Address calculations are first truncated to the effective-address size of the current mode (64-bit mode or compatibility mode), as overridden by any address-size prefix. The result is then zero-extended to the full 64-bit address width.
Posted on 2010-06-13 11:31:33 by SpooK
3.7.5.1      Specifying an Offset in 64-Bit Mode
The offset part of a memory address in 64-bit mode can be specified directly as a
static value or through an address computation made up of one or more of the
following components:
•    Displacement — An 8-bit, 16-bit, or 32-bit value.
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2.2.1.3     Displacement
Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The
ModR/M and SIB displacement sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits.
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In the first manual it says that displacement can be 16 bits in 64-Bit Mode,  in the other one it says it is only 8 or 32!!

Posted on 2010-06-26 23:05:47 by logicman112