MOV  , al

Supposing that CPU data bus is 32 bits, when al value is driven on data bus what will be the value of D31 to D8 lines?
Posted on 2010-07-20 04:51:22 by logicman112
Is this a trick question? the D0-D7 lines will be set to the value of AL, and the other lines will be pulled low.
All lines of both data and address buses are pulled low unless set high by a gating device.
Posted on 2010-07-20 06:13:37 by Homer
Thanks  Homer
Posted on 2010-07-20 07:56:24 by logicman112
Correct me if i'm wrong, i believe maybe you were wondering if a byte write requires reading from ram in order to preserve the nonwritten bytes.
I don't know how this is handled but i guess the memory bus must have some other lines that control the width and position of the data being transmitted, if it's not a dword.
As a side not i think that since the pentium the data lines are 64 bits wide.
Posted on 2010-07-23 17:18:31 by HeLLoWorld
By reading another topic I realize the caches inbetween means that probably memory will ever only need to be read or written on cacheline granularity, so the problem i have in mind must be handled by some protocol on the bus between the processor core and the cache, I'm not sure what you mean by the D0-D32 lines after all.
Posted on 2010-07-23 17:28:21 by HeLLoWorld
Okay, by reading further i realize despite what i said earlier, it is possible to acess bytes individually on the lines outside the processor (for mmio etc). I also learnt the c/be bits do just this, select relevant bytes. One never stops learning. I guess I neglected the chipset/memory subsystem too much in my quest for knowledge.
Posted on 2010-07-23 18:07:14 by HeLLoWorld