How CPU(Intel Core 2 Due) differentiates I/O space access from memory? I am looking for some CPU pins and signals involved.

Besides how PCI protocol separates I/O access from memory? Please explain in terms of PCI bus signals involved in this process.

Are byte enable PCI signals or BE#[3::0] used in an I/O read/write transaction from PCI specification point of view?
Posted on 2010-07-21 07:33:53 by logicman112