10.1
10.1.1
Host Interface
FSB Source Synchronous Transfers
The (G)MCH supports the Intel Core Duo and Intel Core Solo processor subset of the
Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous
transfer is used for the address and data signals.
10.1.2
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
-------------------------------------------------------------------------------------
does anybody know about Northbridge IC of Intel, 82945 and its FSB (front side bus) interface and Enhanced Mode Scaleable Bus? It supports 12 simultaneous outstanding transactions. What does it mean by these simultaneous transactions?

Posted on 2010-08-18 06:33:28 by logicman112