Finally, they put it out of its misery:

August 18, 2010 by Sharon Troia

AMD introduced the 3DNow! ™ instruction set back in the K6-2 days to do Single Instruction Multiple Data (SIMD) instructions, otherwise known as vectorized instructions.  These were mainly used for graphics intensive applications and even audio processing. Since then, we have added many SIMD instruction sets to our processors, such as the widely used Streaming SIMD Extensions (SSE) instruction set and its successive versions.

3DNow! instructions are being deprecated and will not be supported in certain upcoming AMD processors. In those processors, the 3DNow! Instructions feature flag bit will not be set. This is indicated by EDX bit 31 of CPUID function 8000_0001h. This is a good time to remind developers just how important it is to check for features supported at runtime before using them.  We have always recommended this feature check at runtime as a best practice, but it becomes very important now to help prevent your program from failing if it tries to execute this instruction without first checking if the feature is supported.  Around the same time as 3DNow! instructions were developed, programmers were accustomed to using a model of ‘try and catch’ to check if a processor supported an instruction or instruction set.  This is when the application ‘tries’ to execute an instruction to see if it’s available.  If the application receives an Undefined Exception (#UD) from the processor, it believes the instruction set isn’t available.  These types of applications may not do well under newer virtual machines.  That’s subject for another blog though.

There is one exception.  The 3DNow! versions of the PREFETCH and PREFETCHW instructions are now in a class of their own and AMD plans to continue to support them. This can be checked by testing bit 8 of register ECX following a CPUID function 8000_0001 instruction. This feature flag bit is named 3DNowPrefetch in the CPUID Specification.

What does this mean for you? 

If your software used 3DNow! instructions at any point in time you should confirm that you only take that code path after checking to see if the feature is supported during runtime, using CPUID.

Most likely, your code already has another code path to take, such as an SSE path, if 3DNow! instructions are not supported.  To reiterate, make sure that the code uses feature bits to determine when the code should take this path.  If the code uses the vendorID string rather than a feature bit to make the path determination, AMD processors that support SSE may end up taking a slower path as a result.

If you are interested in changing your 3DNow! code to SSE, you can reference Appendix A of the AMD64 Architecture Programmer’s Manual, Volume 5.  It lists the recommended SSE substitutions for those considering porting 3DNow! code to SSE.

Also, note that deprecating 3DNow! instructions or any other instruction set can have an impact on migrating virtual machines between dissimilar hardware. This is another topic unto itself, but VMware addresses this issue here as it relates to 3DNow! and you can reference AMD’s own documentation regarding live migration:

•VMware: Enhanced vMotion Compatibility (EVC) processor support
•Live Migration with AMD-V™ Extended Migration Technology

-Written by Randy VanderHeyden, Member of Technical Staff at AMD and Sharon Troia, Sr. Developer Relations Engineer
Posted on 2010-08-20 04:18:29 by Scali