My question is about Intel Core 2 Duo processor when local APIC is disabled and NMI and INTR pins are connected to an external PIC(programmable interrupt controller). Interrupt comes but how interrupt is acknowledged by CPU on FSB (front side bus)? I mean what signals and pins of the processor will eventually generate an interupt acknowledge cycle (on PCI bus)?
Disregarding the PIC8259A and the more modern APIC, we'll have one or more IRQ pins on the cpu - for the 386+, there are 16 of them. Depending on the chip, they can be triggered on a Rising Edge, a Falling Edge, or both edge transitions.
The behavior of the default ISR for each IRQ will be to signal that interrupt-acknowledge (noting that this behavior is determined by the BIOS firmware). Usually when we replace an ISR with our own, we are HOOKING it such that our new ISR eventually jumps to the original ISR - where the IRQ will be acknowledged.
Hope that helps :)