What is the best way to ensure the cache is clear on an x86 processor? (Besides rebooting the machine. ;)) Both instruction and data cache.
Posted on 2002-02-15 13:01:20 by bitRAKE
From memory the CPUID mnemonic will do that. Its documented somewhere that you use this instruction to clear the cache before running RDTSC so you minimise cache effects.

Regards,

hutch@movsd.com
Posted on 2002-02-15 17:27:48 by hutch--
Not really ;)

CPUID is a serializing instruction, meaning (in substance and practice) that it will "flush" the *pipeline*, and will also wait that all pending operations are completed.

For clearing the caches you must use WBINVD instead.

Greets,
Maverick
Posted on 2002-02-15 18:09:43 by Maverick
or INVD(both this and WBINVD are avail. on 486 only)
Posted on 2002-02-15 18:18:49 by stryker
If I was to write an algorithm that would work on all CPU's to trash the caches - not empty, but put known garbage in them, do you have any suggestions?
Posted on 2002-02-15 18:19:32 by bitRAKE
I'm not sure if this is what you want, this comes from my old link archives about motherboards.

http://www.pcguide.com/ref/mbsys/cache/index.htm

There are references on Cache Write Policy, How Cache works...
Posted on 2002-02-15 18:49:07 by stryker

If I was to write an algorithm that would work on all CPU's to trash the caches - not empty, but put known garbage in them, do you have any suggestions?

Well.. simply execute a very long inlined routine (to trash inst cache), maybe made of all NOP's, and access a very big table, maybe of zero's (to trash data cache). Very big here means level2 cache.

Greets,
Maverick
Posted on 2002-02-15 19:25:24 by Maverick
Maverick, that is kind of what I was thinking. Just curious if that would be enough? I've read much from the Intel/AMD manuals about how they process instructions through the pipeline, and there isn't much detail about the register renaming and out of order execution. Sometimes the instruction sequence doesn't matter and other times they don't get rearranged (it does matter). I'm just curious about how this works exactly. Has anyone seen any docs they think might help?

umberg6007, thanks for the link.
Posted on 2002-02-15 22:22:14 by bitRAKE
To re-synch the pipelines you may use a serializing instruction as XOR EAX,EAX / CPUID.

About doing the whole thing, that involves CPU-model-specific info.. I very much feel that it can be done without problems, but has to be tuned for each specific CPU (expecially in the P6 and Athlon family cases).

If I may ask, I wonder why you need it though.. have to clear some important trace from your CPU that the FBI is after to? ;)

Greets,
Maverick
Posted on 2002-02-16 04:46:58 by Maverick
It sounds like some setup for benchmarking or testing.

Clearing both code and data cache can be done by executing enough code and reading enough data but it would not be fast. This would not matter in benchmarking but it would in more normal code.

Regards,

hutch@movsd.com
Posted on 2002-02-16 08:01:52 by hutch--
For benchmarking ok, in fact, even to the slow version.. but I don't see what's the use for it in normal code anyway, where you may desire a faster version.
A controlled reset may do the trick.. dunno, haven't looked at it seriously.

Check the systems programmers manual for your CPU (e.g. Pentium Vol.3 book) for all the needed informations.
Posted on 2002-02-16 08:08:54 by Maverick
In any case, as I said in my other post, for benchmarking purposes WBINVD is all that is needed.

If you're afraid that Intel/AMD may have some undocumented opcode or way to read the invalidated cache and discover important stuff from there (they wouldn't need to look at the cache in that case to find that info.. when RAM and disk are there to host all of your code :) ), then your only reliable option would be to really use the cache as much as it is necessary to trash away all older information (like overwriting it all).

You may wish to overwrite it seven times, as in hard disks to avoid some specialized company to discover the previously recorded data, in the form of weak analog signals still present.

Greets,
Maverick
Posted on 2002-02-16 08:12:58 by Maverick

You may wish to overwrite it seven times, as in hard disks to avoid some specialized company to discover the previously recorded data, in the form of weak analog signals still present.

Hey, I forgot to add this to the above ---> :grin:

;)

Greets,
Maverick
Posted on 2002-02-16 08:14:40 by Maverick
I am not paranoid. :)

Benchmarks. :grin:
Posted on 2002-02-16 09:59:21 by bitRAKE
I been following this post with a lot of interest cuz just now I am trying to dump cache to index.dat files. (I wrote a program to view and edit index.dat files and it seems these are not updated until reboot or shutdown), therefore I am trying to force the memory dump now.

When I read hutch-- From memory the CPUID mnemonic will do that. I thought haha here's exactly what I need. However I get error 'instruction not accepted in current cpu mode' for both cpuid and rtdsc :(

any help appreciated,
best regards,

czDrillard
Posted on 2002-02-17 14:12:15 by czDrillard
czDrillard, the cache which I speak of is the one inside the CPU - AFAIK, it cannot be dumped to a file. The task you want is a different one all together.
Posted on 2002-02-17 15:06:27 by bitRAKE
Hi umberg :)

or INVD(both this and WBINVD are avail. on 486 only)
Sorry, but INVD should not be used since it will not flush the write-allocated data cache, and in short there will be data corruption if used. Use WBINVD instead. Using of INVD makes sense only during OS initialization, and some other very specific case.

Greets,
Maverick
Posted on 2002-02-17 16:18:32 by Maverick
Write-allocated or not. ;)

I meant that on Pentium or higher (where write-allocation is available) things would get an even higher chance of data corruption than in plain old 486.

Greets,
Maverick
Posted on 2002-02-17 16:19:55 by Maverick

I been following this post with a lot of interest cuz just now I am trying to dump cache to index.dat files. (I wrote a program to view and edit index.dat files and it seems these are not updated until reboot or shutdown), therefore I am trying to force the memory dump now.

When I read hutch-- From memory the CPUID mnemonic will do that. I thought haha here's exactly what I need. However I get error 'instruction not accepted in current cpu mode' for both cpuid and rtdsc :(

any help appreciated,
best regards,

czDrillard


Sorry to disappoint you, but there's no documented way to read and thus save to a file the CPU caches. I'm pretty sure there's no undocumented way as well (would be a sensible waste of chip space to support).

Regarding CPUID, no, it doesn't flush the caches.. at all. It only flushes the pipelines.

I hope that was useful.

Greets,
Mav
Posted on 2002-02-17 16:21:57 by Maverick
I should have posted a warning when using INVD :) he! he! , No problem, Maverick :alright:
Posted on 2002-02-17 17:18:40 by stryker