"...The first instruction that is fetched and executed following a hardware reset is located at physical address FFFFFFF0H...."-------------??intel software developer's manual volume 3??

Why isn't FFFF0H??!! Is that means processor in protected mode after hardware reset?????
Posted on 2001-08-16 00:26:20 by snow
I think both are correct. I recall from one of my books stating that BIOS must be mapped to 2 locations. This if for processors with protect mode. It still resets into real mode.
Posted on 2001-08-16 04:59:15 by eet_1024
Hi ,eet_1024,do you means that:

processor in protected mode--------"during"a hardware reset
processor in real mode---------------"after" a hardware reset

???
Posted on 2001-08-16 07:34:50 by snow
The 386 an up are 32-bit CPUs with 32 bits of addressing at the pinout level (which is what "physical" means). This is unlike the 8086/8088 which had only 20 bits of addressing. The high address puts a bootstrap ROM at the tail end of the memory space. You still boot up in real mode.

If you read further, you'll find that when CS gets reloaded (typically with a far jump), the code (CS:) addresses become normal. If you're still in real mode, the code addresses drop down to the 1M addressing of the 8086.

During a hardware reset, the processor is not executing any code, so there is no mode associated with the reset.
Posted on 2001-08-16 13:59:59 by tank