I am looking at some code and have a couple ( few ) questions
1) What does CDQ do?
2) What does IDIV ECX do?
These are my main problems. Also does anybody know of a good resource that you can search for an explanation of a opcode?
I haven't tried searching the board or google ... yet, I just thought that searching for these would just bring up more confusing code.
Thanks for any help,
gorshing
1) What does CDQ do?
2) What does IDIV ECX do?
These are my main problems. Also does anybody know of a good resource that you can search for an explanation of a opcode?
I haven't tried searching the board or google ... yet, I just thought that searching for these would just bring up more confusing code.
Thanks for any help,
gorshing
CDQ - Convert Double to Quad (386+)
Usage: CDQ
Modifies flags: None
Converts signed DWORD in EAX to a signed quad word in EDX:EAX by extending the high order bit of EAX throughout EDX
-----
IDIV - Signed Integer Division
Usage: IDIV src
Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)
Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AL and the remainder in DX.
Usage: CDQ
Modifies flags: None
Converts signed DWORD in EAX to a signed quad word in EDX:EAX by extending the high order bit of EAX throughout EDX
-----
IDIV - Signed Integer Division
Usage: IDIV src
Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)
Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AL and the remainder in DX.
And for (I)DIV, if src is a DWORD (as it world be using ECX), the 64 bit value in EDX:EAX is divided by src, with the quotient placed in EAX and the remainder in EDX.
MASM32 comes with a quick opcode ref. Otherwise, tons of info on the Intel site. :)
MASM32 comes with a quick opcode ref. Otherwise, tons of info on the Intel site. :)
1 lea esi, offset name ; name is "chad"
2 movsx eax, byte ptr ; ebx is a counter( 0 the first time through ), so looking at c first
3 cdq
4 idiv ecx ; contains 0Ah
So the cdq statement puts all zero's in EDX, correct? Since 'c' is only 63h, it wouldn't be signed
If I am just messing around with characters, nothing binary, hy mess with all these signed opcodes? Isn't positive numbers most significant bit 0 and negitive numbers most significant bit 1 ( granted that the number is within the range, since 63h fits within the 32bit range it's most significant bit is 0 )
So if I divide by 0Ah, then 63h( 'c' ) / Ah, that would put 9 in eax and 9 in edx -- 99/10
I'm looking at somebody elses code and these are the only statements that are confusing me. :(
Thanks again,
gorshing
PS - I apologize for taking baby steps, but I have having a hard time with this, thanks
2 movsx eax, byte ptr ; ebx is a counter( 0 the first time through ), so looking at c first
3 cdq
4 idiv ecx ; contains 0Ah
So the cdq statement puts all zero's in EDX, correct? Since 'c' is only 63h, it wouldn't be signed
If I am just messing around with characters, nothing binary, hy mess with all these signed opcodes? Isn't positive numbers most significant bit 0 and negitive numbers most significant bit 1 ( granted that the number is within the range, since 63h fits within the 32bit range it's most significant bit is 0 )
So if I divide by 0Ah, then 63h( 'c' ) / Ah, that would put 9 in eax and 9 in edx -- 99/10
I'm looking at somebody elses code and these are the only statements that are confusing me. :(
Thanks again,
gorshing
PS - I apologize for taking baby steps, but I have having a hard time with this, thanks
So the cdq statement puts all zero's in EDX, correct? Since 'c' is only 63h, it wouldn't be signed
Yes, if it's sign it will be 0FFFFFFFFh.So if I divide by 0Ah, then 63h( 'c' ) / Ah, that would put 9 in eax and 9 in edx -- 99/10Instead of using cdq you can use sar edx, 1Fh since on some "older cpus" cdq is slow.
mov edx, eax
sar edx, 1Fh