There is an option in ML that turns on timing generation in listing file, but I could find any traces of its action in listings.
I used .686 in my source.
Can anybody post an excerpt from a listing and show me where this timing numbers are?

I assume that MASM doesn't actually analyze how many micro ops each operation takes depending on the processor ( to have some of VTune features in MASM would be nice)
Posted on 2002-07-15 11:36:35 by Sergo
Timing isn't in for 686, it may not ever be in...
Timing on the 686 and above is a tricky thing, and stating this instruction takes that long is no longer relevant.

In some ways, the timing for the 586 (Pentium class chips) is silly, what with there being two execution pipes, doing a total of the clock cycles list won't tell you how long it will actually take. Some instructions will pair up, others won't so a simple listing doesn't work. The same is true of the 686, only much much more so.

The 686 can execute instructions out of order if the processor feels like doing so. If the instructions aren't interdependant then the work carries on. This means a big div in the middle of your code won't stop the memory reads just after it happening (as long as the div won't affect them at any rate). So the timing is a little off!
Also the timing of the 686 needs to consider decode speed, and will be hit much more by caching, and memory bandwidth issues.

To put it simply (from my perspective), the speed of individual instructions is no longer important, the speed of groups of instructions, in certain combinations is.

Posted on 2002-07-15 12:17:24 by Mirno
Yup, times only show up for .586 and lower.

Mirno has a good point. I look at the time as being the MAX needed. Some like DIV and MUL really stand out. But many instructions execute in 1 clock on a 586+. With the pipeline, the next instruction is often executed at the same time, in effect taking 0 clocks. Agner Fog gives a very detailed description in his optimization guide. :)
Posted on 2002-07-15 15:39:19 by S/390