I have gone through a few books but i still cant understand it. Can someone please explain me or give me a link to one?
Posted on 2002-11-09 06:04:12 by clippy
Are you talking about those white sheets of paper that form a book when stacked together ?:grin:

Pages are just 4Kb memory chunks. Pages are also called some dwords that point to these memory chunks. An array of these special dwords forms the "page table". These dwords help to address the data in protected mode. The addressing is somewhat complex: What is visible to us, is the "selector: offset" pair. The "selector" is basically a pointer to the "descriptor table", it "selects" a specific "descriptor". A "descriptor" is a 64 bit entry, which has a lot of info packed in it, the most important being the 32bit address of a segment in memory. We get this address and add the offset, and now we have what is called a "linear address" (which is a 32 bit value). Unfortunately, we are not over yet. When "paging mode" is "on", this "linear address" consists of three components: A "directory" (10 bits), a "page" (10 bits) and an "offset" (12 bits):
1) The "directory" selects an entry from the "page directory". The "page directory" is -like the page table- an array of dwords. Each dword points to another page table.
2) The "page" selects an entry form the "page table" (the "directory" decides which "page table"). This entry is a dword also called a "page", and its high order 20 bits is finally the physical address of the memory chunk also called a "page"
3) The "offset" is just a value we add to the "page" to get to the actual physical memory.

Edit: Since the "offset" is 12 bits, the "page size" is 2^12 = 4096 bytes. Since the "page" includes a 20 bit address, this address may be 2^20 = 1MB. So, we have 1MB * 4KB = the infamous 4GB addressing space.
Posted on 2002-11-09 08:02:47 by micmic
The old 386 manual does a pretty good job of describing pages, etc. Here's an HTML version:

http://library.n0i.net/hardware/intel80386-programmer-manual/Chap5.html

:)
Posted on 2002-11-09 11:35:46 by S/390
said

Pages are just 4Kb memory chunks

---

Well, actually, it depends of the architecture u are working with. 4096 bytes is for the x86.
Posted on 2002-11-09 13:42:51 by amcd
A page is the smallest block of memory managed by a virtual memory system.

With the appropriate hardware, a page which represents a memory block (e.g., the 4K address range 1000h - 1FFFh) can be located in any (aligned) chunk of real RAM. Pages which represent consecutive memory blocks aren't guaranteed to be consecutive in real RAM.

With appropriate software and support hardware, the pages can be temporarily stored on a disk and retrieved when needed.
Posted on 2002-11-09 23:29:53 by tenkey
Just a short note, on intel processors page size can also be 4mb, and 2mb on pentium pro+. In fact, some of Windows(at least win2k)' kernel pages are 4mb.
Posted on 2002-11-10 00:14:44 by C.Z.
Another definition of page...

Some processors split an address into two parts. The more significant part is called the page number and the less significant part is the offset into the page. Typical 8- and 16-bit processors use 16-bit addresses that fit neatly into two 8-bit bytes. On these processors, a 256 byte memory block addressed by the same upper 8-bits of the address is often called a page.
Posted on 2002-11-10 02:01:00 by tenkey
I think you don't ned to 'exactly' understand how the page mechanism works.

I know it only theoretically and doesn't need it in my programms.:tongue:
Posted on 2002-11-10 04:28:11 by TCT
thanks for the load of replies everyone.

S/390,
that manual looks pretty informative. I will read through it as soon as i get a bit of time.

One more thing i dont understand is that whats the use of having 4mb or 2mb pages cause if you allocate say 1 byte of memory then if the page size is 4 mb then you would be wasting the rest of the memory cause thats the smallest amount of memory you can allocate.
So why do processors even allow having such huge pages? Whats the advantage of having it?
Posted on 2002-11-12 01:13:00 by clippy
Source: Dictionary.com:

Page
n.
...
3. Computer Science. A quantity of memory storage equal to between 512 and 4,096 bytes.
Posted on 2002-11-12 07:57:45 by iblis
Yup, that old manual is still one of my favs. Chips themselves today are faster, and they've added things like pipelines, out of order exec, and better branch prediction. There are some new instructions today, and most of the old ones run in fewer clocks. But at the core, very little has changed in the 32 bit "concept" since the 386, and this is one of the best books that I've seen in describing that concept. I've got the old .TXT version, but this site did a pretty good job of porting it to HTML. Here's a link to the top:

http://library.n0i.net/hardware/intel80386-programmer-manual/

As for your question about page size, you need to remember why we have pages in the first place. They have nothing to do with memory allocation, but rather memory management. They only exist to support a "virtual memory" environment. where the hardware and OS cooperate in translating virtual addresses to real addresses, and in moving "idle" pages between memory and disk, and back when needed.

Think of it as the OS breaking your entire program (both instructions and data) into chunks that it can manage.

:)
Posted on 2002-11-12 10:53:14 by S/390
You have to remember that there is a silicon cost associated with the number of bits in a bus. If you want full access to the whole 4GB address range, you need to lay a full 32 bit bus all through your entire chip (anywhere that accesses it). If you decide that you can reasonably fit all that you need in a chuck of size 2^X bits, when fetching that chunk you only need a 33 - X bit bus. And when accessing data within that chunk, you only need an X bit bus. This can vastly reduce the size of certain parts of the chip (and ask anyone who does layout how tough it can be trying to fit chunky busses out, and coming to time).

It is essentially an exercise in simplification, there is a "waste" overhead, but that can be lived with. The same principal appplies to the FAT disk management system, you adopt a cluster size of X bytes, because the hard disk is so massive, chances are you wont be trying to store 107,374,182,400 1 byte files on your 1GB disk. Most files will fill several clusters, and then waste a bit of 1. If you choose 4 MB pages, its because you are targeting the OS towards big tasks (enterprise class computing with monster databases etc.), and smaller tasks will have to was some of the space.

Mirno
Posted on 2002-11-12 11:32:20 by Mirno
Source: Dictionary.com:

Page
n.
...
3. Computer Science. A quantity of memory storage equal to between 512 and 4,096 bytes.

Bogus definition. It sets arbitrary limits and doesn't hint at the use of pages in a virtual memory system.

Another reason for being a bad definition -- Intel defines a PAGE alignment (in SEGMENT directives) as 256 bytes, which is consistent with my second definition.
Posted on 2002-11-12 16:36:01 by tenkey
Now, now, before you go discrediting Meriam-Webster, realize that's just one definition. It could very well be true in its own context.

Here are more definitions. Have fun.
Posted on 2002-11-12 18:55:57 by iblis

Are you talking about those white sheets of paper that form a book when stacked together ?:grin:

Pages are just 4Kb memory chunks. Pages are also called some dwords that point to these memory chunks. An array of these special dwords forms the "page table". These dwords help to address the data in protected mode. The addressing is somewhat complex: What is visible to us, is the "selector: offset" pair. The "selector" is basically a pointer to the "descriptor table", it "selects" a specific "descriptor". A "descriptor" is a 64 bit entry, which has a lot of info packed in it, the most important being the 32bit address of a segment in memory. We get this address and add the offset, and now we have what is called a "linear address" (which is a 32 bit value). Unfortunately, we are not over yet. When "paging mode" is "on", this "linear address" consists of three components: A "directory" (10 bits), a "page" (10 bits) and an "offset" (12 bits):
1) The "directory" selects an entry from the "page directory". The "page directory" is -like the page table- an array of dwords. Each dword points to another page table.
2) The "page" selects an entry form the "page table" (the "directory" decides which "page table"). This entry is a dword also called a "page", and its high order 20 bits is finally the physical address of the memory chunk also called a "page"
3) The "offset" is just a value we add to the "page" to get to the actual physical memory.

Edit: Since the "offset" is 12 bits, the "page size" is 2^12 = 4096 bytes. Since the "page" includes a 20 bit address, this address may be 2^20 = 1MB. So, we have 1MB * 4KB = the infamous 4GB addressing space.


according to the info, the 12bits like a books directory(contents 4096 entries), while the other 20bits is the books contents page(each page has 1MB content)? am i right in thinking this way?
Posted on 2002-11-12 19:39:09 by baumann
When we have the "linear address" (directory (10bits) - page (10bits) - offset(12bits)):
The whole memory will be a library. The directory will select a specific book ( = page table). After we have the book, page will select a specific page of that book. And the offset will select a specific byte (= letter) in that page. 4096 (4KB) is the number of letters in the page. 1048576 (1MB) is the total number of pages in all the books of the library.
Posted on 2002-11-13 02:19:04 by micmic